58 lines
2.0 KiB
Plaintext
58 lines
2.0 KiB
Plaintext
Intel Service Layer Driver for Stratix10 SoC
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============================================
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Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
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processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
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configured from HPS, there needs to be a way for HPS to notify SDM the
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location and size of the configuration data. Then SDM will get the
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configuration data from that location and perform the FPGA configuration.
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To meet the whole system security needs and support virtual machine requesting
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communication with SDM, only the secure world of software (EL3, Exception
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Layer 3) can interface with SDM. All software entities running on other
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exception layers must channel through the EL3 software whenever it needs
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service from SDM.
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Intel Stratix10 service layer driver, running at privileged exception level
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(EL1, Exception Layer 1), interfaces with the service providers and provides
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the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer
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driver also manages secure monitor call (SMC) to communicate with secure monitor
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code running in EL3.
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Required properties:
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-------------------
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The svc node has the following mandatory properties, must be located under
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the firmware node.
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- compatible: "intel,stratix10-svc" or "intel,agilex-svc"
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- method: smc or hvc
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smc - Secure Monitor Call
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hvc - Hypervisor Call
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- memory-region:
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phandle to the reserved memory node. See
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Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
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for details
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Example:
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-------
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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service_reserved: svcbuffer@0 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x0 0x0 0x1000000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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firmware {
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svc {
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compatible = "intel,stratix10-svc";
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method = "smc";
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memory-region = <&service_reserved>;
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};
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};
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