469 lines
12 KiB
C
469 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
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*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* With some ideas taken from pinctrl-samsung:
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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* Copyright (c) 2012 Linaro Ltd
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* https://www.linaro.org
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*
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* and pinctrl-at91:
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* Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*/
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#ifndef _PINCTRL_ROCKCHIP_H
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#define _PINCTRL_ROCKCHIP_H
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#define RK_GPIO0_A0 0
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#define RK_GPIO0_A1 1
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#define RK_GPIO0_A2 2
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#define RK_GPIO0_A3 3
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#define RK_GPIO0_A4 4
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#define RK_GPIO0_A5 5
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#define RK_GPIO0_A6 6
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#define RK_GPIO0_A7 7
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#define RK_GPIO0_B0 8
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#define RK_GPIO0_B1 9
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#define RK_GPIO0_B2 10
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#define RK_GPIO0_B3 11
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#define RK_GPIO0_B4 12
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#define RK_GPIO0_B5 13
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#define RK_GPIO0_B6 14
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#define RK_GPIO0_B7 15
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#define RK_GPIO0_C0 16
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#define RK_GPIO0_C1 17
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#define RK_GPIO0_C2 18
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#define RK_GPIO0_C3 19
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#define RK_GPIO0_C4 20
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#define RK_GPIO0_C5 21
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#define RK_GPIO0_C6 22
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#define RK_GPIO0_C7 23
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#define RK_GPIO0_D0 24
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#define RK_GPIO0_D1 25
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#define RK_GPIO0_D2 26
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#define RK_GPIO0_D3 27
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#define RK_GPIO0_D4 28
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#define RK_GPIO0_D5 29
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#define RK_GPIO0_D6 30
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#define RK_GPIO0_D7 31
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#define RK_GPIO1_A0 32
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#define RK_GPIO1_A1 33
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#define RK_GPIO1_A2 34
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#define RK_GPIO1_A3 35
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#define RK_GPIO1_A4 36
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#define RK_GPIO1_A5 37
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#define RK_GPIO1_A6 38
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#define RK_GPIO1_A7 39
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#define RK_GPIO1_B0 40
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#define RK_GPIO1_B1 41
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#define RK_GPIO1_B2 42
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#define RK_GPIO1_B3 43
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#define RK_GPIO1_B4 44
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#define RK_GPIO1_B5 45
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#define RK_GPIO1_B6 46
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#define RK_GPIO1_B7 47
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#define RK_GPIO1_C0 48
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#define RK_GPIO1_C1 49
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#define RK_GPIO1_C2 50
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#define RK_GPIO1_C3 51
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#define RK_GPIO1_C4 52
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#define RK_GPIO1_C5 53
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#define RK_GPIO1_C6 54
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#define RK_GPIO1_C7 55
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#define RK_GPIO1_D0 56
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#define RK_GPIO1_D1 57
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#define RK_GPIO1_D2 58
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#define RK_GPIO1_D3 59
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#define RK_GPIO1_D4 60
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#define RK_GPIO1_D5 61
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#define RK_GPIO1_D6 62
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#define RK_GPIO1_D7 63
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#define RK_GPIO2_A0 64
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#define RK_GPIO2_A1 65
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#define RK_GPIO2_A2 66
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#define RK_GPIO2_A3 67
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#define RK_GPIO2_A4 68
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#define RK_GPIO2_A5 69
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#define RK_GPIO2_A6 70
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#define RK_GPIO2_A7 71
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#define RK_GPIO2_B0 72
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#define RK_GPIO2_B1 73
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#define RK_GPIO2_B2 74
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#define RK_GPIO2_B3 75
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#define RK_GPIO2_B4 76
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#define RK_GPIO2_B5 77
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#define RK_GPIO2_B6 78
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#define RK_GPIO2_B7 79
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#define RK_GPIO2_C0 80
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#define RK_GPIO2_C1 81
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#define RK_GPIO2_C2 82
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#define RK_GPIO2_C3 83
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#define RK_GPIO2_C4 84
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#define RK_GPIO2_C5 85
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#define RK_GPIO2_C6 86
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#define RK_GPIO2_C7 87
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#define RK_GPIO2_D0 88
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#define RK_GPIO2_D1 89
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#define RK_GPIO2_D2 90
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#define RK_GPIO2_D3 91
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#define RK_GPIO2_D4 92
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#define RK_GPIO2_D5 93
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#define RK_GPIO2_D6 94
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#define RK_GPIO2_D7 95
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#define RK_GPIO3_A0 96
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#define RK_GPIO3_A1 97
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#define RK_GPIO3_A2 98
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#define RK_GPIO3_A3 99
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#define RK_GPIO3_A4 100
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#define RK_GPIO3_A5 101
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#define RK_GPIO3_A6 102
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#define RK_GPIO3_A7 103
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#define RK_GPIO3_B0 104
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#define RK_GPIO3_B1 105
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#define RK_GPIO3_B2 106
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#define RK_GPIO3_B3 107
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#define RK_GPIO3_B4 108
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#define RK_GPIO3_B5 109
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#define RK_GPIO3_B6 110
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#define RK_GPIO3_B7 111
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#define RK_GPIO3_C0 112
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#define RK_GPIO3_C1 113
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#define RK_GPIO3_C2 114
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#define RK_GPIO3_C3 115
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#define RK_GPIO3_C4 116
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#define RK_GPIO3_C5 117
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#define RK_GPIO3_C6 118
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#define RK_GPIO3_C7 119
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#define RK_GPIO3_D0 120
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#define RK_GPIO3_D1 121
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#define RK_GPIO3_D2 122
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#define RK_GPIO3_D3 123
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#define RK_GPIO3_D4 124
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#define RK_GPIO3_D5 125
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#define RK_GPIO3_D6 126
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#define RK_GPIO3_D7 127
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#define RK_GPIO4_A0 128
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#define RK_GPIO4_A1 129
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#define RK_GPIO4_A2 130
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#define RK_GPIO4_A3 131
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#define RK_GPIO4_A4 132
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#define RK_GPIO4_A5 133
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#define RK_GPIO4_A6 134
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#define RK_GPIO4_A7 135
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#define RK_GPIO4_B0 136
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#define RK_GPIO4_B1 137
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#define RK_GPIO4_B2 138
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#define RK_GPIO4_B3 139
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#define RK_GPIO4_B4 140
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#define RK_GPIO4_B5 141
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#define RK_GPIO4_B6 142
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#define RK_GPIO4_B7 143
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#define RK_GPIO4_C0 144
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#define RK_GPIO4_C1 145
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#define RK_GPIO4_C2 146
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#define RK_GPIO4_C3 147
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#define RK_GPIO4_C4 148
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#define RK_GPIO4_C5 149
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#define RK_GPIO4_C6 150
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#define RK_GPIO4_C7 151
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#define RK_GPIO4_D0 152
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#define RK_GPIO4_D1 153
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#define RK_GPIO4_D2 154
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#define RK_GPIO4_D3 155
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#define RK_GPIO4_D4 156
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#define RK_GPIO4_D5 157
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#define RK_GPIO4_D6 158
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#define RK_GPIO4_D7 159
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enum rockchip_pinctrl_type {
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PX30,
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RV1108,
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RV1126,
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RK2928,
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RK3066B,
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RK3128,
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RK3188,
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RK3288,
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RK3308,
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RK3328,
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RK3368,
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RK3399,
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RK3568,
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RK3588,
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};
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/**
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* struct rockchip_gpio_regs
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* @port_dr: data register
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* @port_ddr: data direction register
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* @int_en: interrupt enable
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* @int_mask: interrupt mask
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* @int_type: interrupt trigger type, such as high, low, edge trriger type.
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* @int_polarity: interrupt polarity enable register
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* @int_bothedge: interrupt bothedge enable register
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* @int_status: interrupt status register
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* @int_rawstatus: int_status = int_rawstatus & int_mask
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* @debounce: enable debounce for interrupt signal
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* @dbclk_div_en: enable divider for debounce clock
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* @dbclk_div_con: setting for divider of debounce clock
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* @port_eoi: end of interrupt of the port
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* @ext_port: port data from external
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* @version_id: controller version register
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*/
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struct rockchip_gpio_regs {
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u32 port_dr;
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u32 port_ddr;
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u32 int_en;
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u32 int_mask;
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u32 int_type;
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u32 int_polarity;
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u32 int_bothedge;
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u32 int_status;
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u32 int_rawstatus;
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u32 debounce;
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u32 dbclk_div_en;
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u32 dbclk_div_con;
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u32 port_eoi;
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u32 ext_port;
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u32 version_id;
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};
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/**
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* struct rockchip_iomux
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* @type: iomux variant using IOMUX_* constants
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* @offset: if initialized to -1 it will be autocalculated, by specifying
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* an initial offset value the relevant source offset can be reset
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* to a new value for autocalculating the following iomux registers.
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*/
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struct rockchip_iomux {
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int type;
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int offset;
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};
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/*
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* enum type index corresponding to rockchip_perpin_drv_list arrays index.
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*/
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enum rockchip_pin_drv_type {
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DRV_TYPE_IO_DEFAULT = 0,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_1V8_3V0_AUTO,
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DRV_TYPE_IO_3V3_ONLY,
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DRV_TYPE_MAX
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};
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/*
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* enum type index corresponding to rockchip_pull_list arrays index.
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*/
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enum rockchip_pin_pull_type {
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PULL_TYPE_IO_DEFAULT = 0,
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PULL_TYPE_IO_1V8_ONLY,
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PULL_TYPE_MAX
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};
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/**
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* struct rockchip_drv
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* @drv_type: drive strength variant using rockchip_perpin_drv_type
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* @offset: if initialized to -1 it will be autocalculated, by specifying
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* an initial offset value the relevant source offset can be reset
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* to a new value for autocalculating the following drive strength
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* registers. if used chips own cal_drv func instead to calculate
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* registers offset, the variant could be ignored.
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*/
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struct rockchip_drv {
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enum rockchip_pin_drv_type drv_type;
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int offset;
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};
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/**
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* struct rockchip_pin_bank
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* @dev: the pinctrl device bind to the bank
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* @reg_base: register base of the gpio bank
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* @regmap_pull: optional separate register for additional pull settings
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* @clk: clock of the gpio bank
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* @db_clk: clock of the gpio debounce
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* @irq: interrupt of the gpio bank
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* @saved_masks: Saved content of GPIO_INTEN at suspend time.
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* @pin_base: first pin number
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* @nr_pins: number of pins in this bank
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* @name: name of the bank
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* @bank_num: number of the bank, to account for holes
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* @iomux: array describing the 4 iomux sources of the bank
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* @drv: array describing the 4 drive strength sources of the bank
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* @pull_type: array describing the 4 pull type sources of the bank
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* @valid: is all necessary information present
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* @of_node: dt node of this bank
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* @drvdata: common pinctrl basedata
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* @domain: irqdomain of the gpio bank
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* @gpio_chip: gpiolib chip
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* @grange: gpio range
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* @slock: spinlock for the gpio bank
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* @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode
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* @recalced_mask: bit mask to indicate a need to recalulate the mask
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* @route_mask: bits describing the routing pins of per bank
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* @deferred_output: gpio output settings to be done after gpio bank probed
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* @deferred_lock: mutex for the deferred_output shared btw gpio and pinctrl
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*/
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struct rockchip_pin_bank {
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struct device *dev;
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void __iomem *reg_base;
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struct regmap *regmap_pull;
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struct clk *clk;
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struct clk *db_clk;
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int irq;
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u32 saved_masks;
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u32 pin_base;
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u8 nr_pins;
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char *name;
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u8 bank_num;
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struct rockchip_iomux iomux[4];
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struct rockchip_drv drv[4];
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enum rockchip_pin_pull_type pull_type[4];
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bool valid;
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struct device_node *of_node;
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struct rockchip_pinctrl *drvdata;
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struct irq_domain *domain;
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struct gpio_chip gpio_chip;
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struct pinctrl_gpio_range grange;
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raw_spinlock_t slock;
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const struct rockchip_gpio_regs *gpio_regs;
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u32 gpio_type;
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u32 toggle_edge_mode;
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u32 recalced_mask;
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u32 route_mask;
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struct list_head deferred_pins;
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struct mutex deferred_lock;
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};
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/**
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* struct rockchip_mux_recalced_data: represent a pin iomux data.
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* @num: bank number.
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* @pin: pin number.
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* @bit: index at register.
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* @reg: register offset.
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* @mask: mask bit
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*/
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struct rockchip_mux_recalced_data {
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u8 num;
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u8 pin;
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u32 reg;
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u8 bit;
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u8 mask;
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};
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enum rockchip_mux_route_location {
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ROCKCHIP_ROUTE_SAME = 0,
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ROCKCHIP_ROUTE_PMU,
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ROCKCHIP_ROUTE_GRF,
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};
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/**
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* struct rockchip_mux_recalced_data: represent a pin iomux data.
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* @bank_num: bank number.
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* @pin: index at register or used to calc index.
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* @func: the min pin.
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* @route_location: the mux route location (same, pmu, grf).
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* @route_offset: the max pin.
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* @route_val: the register offset.
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*/
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struct rockchip_mux_route_data {
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u8 bank_num;
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u8 pin;
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u8 func;
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enum rockchip_mux_route_location route_location;
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u32 route_offset;
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u32 route_val;
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};
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struct rockchip_pin_ctrl {
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struct rockchip_pin_bank *pin_banks;
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u32 nr_banks;
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u32 nr_pins;
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char *label;
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enum rockchip_pinctrl_type type;
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int grf_mux_offset;
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int pmu_mux_offset;
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int grf_drv_offset;
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int pmu_drv_offset;
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struct rockchip_mux_recalced_data *iomux_recalced;
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u32 niomux_recalced;
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struct rockchip_mux_route_data *iomux_routes;
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u32 niomux_routes;
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int (*pull_calc_reg)(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit);
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int (*drv_calc_reg)(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit);
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int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit);
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};
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struct rockchip_pin_config {
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unsigned int func;
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unsigned long *configs;
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unsigned int nconfigs;
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};
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enum pin_config_param;
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struct rockchip_pin_deferred {
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struct list_head head;
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unsigned int pin;
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enum pin_config_param param;
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u32 arg;
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};
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/**
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* struct rockchip_pin_group: represent group of pins of a pinmux function.
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* @name: name of the pin group, used to lookup the group.
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* @pins: the pins included in this group.
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* @npins: number of pins included in this group.
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* @data: local pin configuration
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*/
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struct rockchip_pin_group {
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const char *name;
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unsigned int npins;
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unsigned int *pins;
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struct rockchip_pin_config *data;
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};
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/**
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* struct rockchip_pmx_func: represent a pin function.
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* @name: name of the pin function, used to lookup the function.
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* @groups: one or more names of pin groups that provide this function.
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* @ngroups: number of groups included in @groups.
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*/
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struct rockchip_pmx_func {
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const char *name;
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const char **groups;
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u8 ngroups;
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};
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struct rockchip_pinctrl {
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struct regmap *regmap_base;
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int reg_size;
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struct regmap *regmap_pull;
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struct regmap *regmap_pmu;
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struct device *dev;
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struct rockchip_pin_ctrl *ctrl;
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struct pinctrl_desc pctl;
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struct pinctrl_dev *pctl_dev;
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struct rockchip_pin_group *groups;
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unsigned int ngroups;
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struct rockchip_pmx_func *functions;
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unsigned int nfunctions;
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};
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#endif
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