725 lines
18 KiB
C
725 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* Based on sun4i_backend.c, which is:
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* Copyright (C) 2015 Free Electrons
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* Copyright (C) 2015 NextThing Co
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*/
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#include <linux/component.h>
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_graph.h>
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#include <linux/reset.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_framebuffer.h>
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#include <drm/drm_gem_dma_helper.h>
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#include <drm/drm_probe_helper.h>
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#include "sun4i_drv.h"
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#include "sun8i_mixer.h"
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#include "sun8i_ui_layer.h"
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#include "sun8i_vi_layer.h"
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#include "sunxi_engine.h"
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struct de2_fmt_info {
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u32 drm_fmt;
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u32 de2_fmt;
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};
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static const struct de2_fmt_info de2_formats[] = {
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{
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.drm_fmt = DRM_FORMAT_ARGB8888,
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.de2_fmt = SUN8I_MIXER_FBFMT_ARGB8888,
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},
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{
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.drm_fmt = DRM_FORMAT_ABGR8888,
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.de2_fmt = SUN8I_MIXER_FBFMT_ABGR8888,
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},
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{
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.drm_fmt = DRM_FORMAT_RGBA8888,
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.de2_fmt = SUN8I_MIXER_FBFMT_RGBA8888,
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},
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{
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.drm_fmt = DRM_FORMAT_BGRA8888,
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.de2_fmt = SUN8I_MIXER_FBFMT_BGRA8888,
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},
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{
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.drm_fmt = DRM_FORMAT_XRGB8888,
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.de2_fmt = SUN8I_MIXER_FBFMT_XRGB8888,
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},
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{
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.drm_fmt = DRM_FORMAT_XBGR8888,
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.de2_fmt = SUN8I_MIXER_FBFMT_XBGR8888,
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},
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{
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.drm_fmt = DRM_FORMAT_RGBX8888,
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.de2_fmt = SUN8I_MIXER_FBFMT_RGBX8888,
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},
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{
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.drm_fmt = DRM_FORMAT_BGRX8888,
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.de2_fmt = SUN8I_MIXER_FBFMT_BGRX8888,
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},
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{
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.drm_fmt = DRM_FORMAT_RGB888,
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.de2_fmt = SUN8I_MIXER_FBFMT_RGB888,
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},
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{
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.drm_fmt = DRM_FORMAT_BGR888,
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.de2_fmt = SUN8I_MIXER_FBFMT_BGR888,
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},
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{
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.drm_fmt = DRM_FORMAT_RGB565,
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.de2_fmt = SUN8I_MIXER_FBFMT_RGB565,
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},
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{
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.drm_fmt = DRM_FORMAT_BGR565,
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.de2_fmt = SUN8I_MIXER_FBFMT_BGR565,
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},
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{
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.drm_fmt = DRM_FORMAT_ARGB4444,
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.de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444,
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},
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{
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/* for DE2 VI layer which ignores alpha */
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.drm_fmt = DRM_FORMAT_XRGB4444,
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.de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444,
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},
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{
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.drm_fmt = DRM_FORMAT_ABGR4444,
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.de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
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},
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{
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/* for DE2 VI layer which ignores alpha */
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.drm_fmt = DRM_FORMAT_XBGR4444,
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.de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444,
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},
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{
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.drm_fmt = DRM_FORMAT_RGBA4444,
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.de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
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},
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{
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/* for DE2 VI layer which ignores alpha */
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.drm_fmt = DRM_FORMAT_RGBX4444,
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.de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444,
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},
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{
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.drm_fmt = DRM_FORMAT_BGRA4444,
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.de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
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},
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{
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/* for DE2 VI layer which ignores alpha */
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.drm_fmt = DRM_FORMAT_BGRX4444,
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.de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444,
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},
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{
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.drm_fmt = DRM_FORMAT_ARGB1555,
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.de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
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},
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{
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/* for DE2 VI layer which ignores alpha */
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.drm_fmt = DRM_FORMAT_XRGB1555,
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.de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555,
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},
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{
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.drm_fmt = DRM_FORMAT_ABGR1555,
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.de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
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},
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{
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/* for DE2 VI layer which ignores alpha */
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.drm_fmt = DRM_FORMAT_XBGR1555,
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.de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555,
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},
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{
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.drm_fmt = DRM_FORMAT_RGBA5551,
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.de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
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},
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{
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/* for DE2 VI layer which ignores alpha */
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.drm_fmt = DRM_FORMAT_RGBX5551,
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.de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551,
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},
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{
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.drm_fmt = DRM_FORMAT_BGRA5551,
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.de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
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},
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{
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/* for DE2 VI layer which ignores alpha */
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.drm_fmt = DRM_FORMAT_BGRX5551,
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.de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551,
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},
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{
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.drm_fmt = DRM_FORMAT_ARGB2101010,
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.de2_fmt = SUN8I_MIXER_FBFMT_ARGB2101010,
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},
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{
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.drm_fmt = DRM_FORMAT_ABGR2101010,
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.de2_fmt = SUN8I_MIXER_FBFMT_ABGR2101010,
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},
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{
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.drm_fmt = DRM_FORMAT_RGBA1010102,
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.de2_fmt = SUN8I_MIXER_FBFMT_RGBA1010102,
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},
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{
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.drm_fmt = DRM_FORMAT_BGRA1010102,
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.de2_fmt = SUN8I_MIXER_FBFMT_BGRA1010102,
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},
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{
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.drm_fmt = DRM_FORMAT_UYVY,
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.de2_fmt = SUN8I_MIXER_FBFMT_UYVY,
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},
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{
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.drm_fmt = DRM_FORMAT_VYUY,
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.de2_fmt = SUN8I_MIXER_FBFMT_VYUY,
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},
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{
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.drm_fmt = DRM_FORMAT_YUYV,
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.de2_fmt = SUN8I_MIXER_FBFMT_YUYV,
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},
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{
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.drm_fmt = DRM_FORMAT_YVYU,
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.de2_fmt = SUN8I_MIXER_FBFMT_YVYU,
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},
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{
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.drm_fmt = DRM_FORMAT_NV16,
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.de2_fmt = SUN8I_MIXER_FBFMT_NV16,
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},
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{
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.drm_fmt = DRM_FORMAT_NV61,
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.de2_fmt = SUN8I_MIXER_FBFMT_NV61,
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},
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{
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.drm_fmt = DRM_FORMAT_NV12,
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.de2_fmt = SUN8I_MIXER_FBFMT_NV12,
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},
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{
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.drm_fmt = DRM_FORMAT_NV21,
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.de2_fmt = SUN8I_MIXER_FBFMT_NV21,
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},
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{
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.drm_fmt = DRM_FORMAT_YUV422,
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.de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
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},
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{
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.drm_fmt = DRM_FORMAT_YUV420,
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.de2_fmt = SUN8I_MIXER_FBFMT_YUV420,
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},
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{
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.drm_fmt = DRM_FORMAT_YUV411,
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.de2_fmt = SUN8I_MIXER_FBFMT_YUV411,
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},
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{
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.drm_fmt = DRM_FORMAT_YVU422,
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.de2_fmt = SUN8I_MIXER_FBFMT_YUV422,
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},
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{
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.drm_fmt = DRM_FORMAT_YVU420,
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.de2_fmt = SUN8I_MIXER_FBFMT_YUV420,
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},
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{
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.drm_fmt = DRM_FORMAT_YVU411,
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.de2_fmt = SUN8I_MIXER_FBFMT_YUV411,
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},
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{
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.drm_fmt = DRM_FORMAT_P010,
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.de2_fmt = SUN8I_MIXER_FBFMT_P010_YUV,
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},
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{
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.drm_fmt = DRM_FORMAT_P210,
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.de2_fmt = SUN8I_MIXER_FBFMT_P210_YUV,
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},
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};
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int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(de2_formats); ++i)
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if (de2_formats[i].drm_fmt == format) {
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*hw_format = de2_formats[i].de2_fmt;
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return 0;
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}
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return -EINVAL;
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}
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static void sun8i_mixer_commit(struct sunxi_engine *engine)
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{
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DRM_DEBUG_DRIVER("Committing changes\n");
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regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
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SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
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}
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static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
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struct sunxi_engine *engine)
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{
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struct drm_plane **planes;
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struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
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int i;
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planes = devm_kcalloc(drm->dev,
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mixer->cfg->vi_num + mixer->cfg->ui_num + 1,
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sizeof(*planes), GFP_KERNEL);
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if (!planes)
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return ERR_PTR(-ENOMEM);
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for (i = 0; i < mixer->cfg->vi_num; i++) {
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struct sun8i_vi_layer *layer;
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layer = sun8i_vi_layer_init_one(drm, mixer, i);
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if (IS_ERR(layer)) {
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dev_err(drm->dev,
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"Couldn't initialize overlay plane\n");
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return ERR_CAST(layer);
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}
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planes[i] = &layer->plane;
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}
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for (i = 0; i < mixer->cfg->ui_num; i++) {
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struct sun8i_ui_layer *layer;
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layer = sun8i_ui_layer_init_one(drm, mixer, i);
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if (IS_ERR(layer)) {
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dev_err(drm->dev, "Couldn't initialize %s plane\n",
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i ? "overlay" : "primary");
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return ERR_CAST(layer);
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}
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planes[mixer->cfg->vi_num + i] = &layer->plane;
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}
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return planes;
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}
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static void sun8i_mixer_mode_set(struct sunxi_engine *engine,
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const struct drm_display_mode *mode)
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{
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struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
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u32 bld_base, size, val;
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bool interlaced;
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bld_base = sun8i_blender_base(mixer);
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interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
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size = SUN8I_MIXER_SIZE(mode->hdisplay, mode->vdisplay);
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DRM_DEBUG_DRIVER("Updating global size W: %u H: %u\n",
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mode->hdisplay, mode->vdisplay);
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regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_SIZE, size);
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regmap_write(engine->regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size);
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if (interlaced)
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val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED;
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else
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val = 0;
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regmap_update_bits(engine->regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base),
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SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, val);
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DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
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interlaced ? "on" : "off");
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}
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static const struct sunxi_engine_ops sun8i_engine_ops = {
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.commit = sun8i_mixer_commit,
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.layers_init = sun8i_layers_init,
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.mode_set = sun8i_mixer_mode_set,
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};
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static const struct regmap_config sun8i_mixer_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = 0xffffc, /* guessed */
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};
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static int sun8i_mixer_of_get_id(struct device_node *node)
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{
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struct device_node *ep, *remote;
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struct of_endpoint of_ep;
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/* Output port is 1, and we want the first endpoint. */
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ep = of_graph_get_endpoint_by_regs(node, 1, -1);
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if (!ep)
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return -EINVAL;
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remote = of_graph_get_remote_endpoint(ep);
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of_node_put(ep);
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if (!remote)
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return -EINVAL;
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of_graph_parse_endpoint(remote, &of_ep);
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of_node_put(remote);
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return of_ep.id;
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}
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static int sun8i_mixer_bind(struct device *dev, struct device *master,
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void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct drm_device *drm = data;
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struct sun4i_drv *drv = drm->dev_private;
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struct sun8i_mixer *mixer;
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void __iomem *regs;
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unsigned int base;
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int plane_cnt;
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int i, ret;
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/*
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* The mixer uses single 32-bit register to store memory
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* addresses, so that it cannot deal with 64-bit memory
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* addresses.
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* Restrict the DMA mask so that the mixer won't be
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* allocated some memory that is too high.
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*/
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ret = dma_set_mask(dev, DMA_BIT_MASK(32));
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if (ret) {
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dev_err(dev, "Cannot do 32-bit DMA.\n");
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return ret;
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}
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mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
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if (!mixer)
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return -ENOMEM;
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dev_set_drvdata(dev, mixer);
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mixer->engine.ops = &sun8i_engine_ops;
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mixer->engine.node = dev->of_node;
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if (of_find_property(dev->of_node, "iommus", NULL)) {
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/*
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* This assume we have the same DMA constraints for
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* all our the mixers in our pipeline. This sounds
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* bad, but it has always been the case for us, and
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* DRM doesn't do per-device allocation either, so we
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* would need to fix DRM first...
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*/
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ret = of_dma_configure(drm->dev, dev->of_node, true);
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if (ret)
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return ret;
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}
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/*
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* While this function can fail, we shouldn't do anything
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* if this happens. Some early DE2 DT entries don't provide
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* mixer id but work nevertheless because matching between
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* TCON and mixer is done by comparing node pointers (old
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* way) instead comparing ids. If this function fails and
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* id is needed, it will fail during id matching anyway.
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*/
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mixer->engine.id = sun8i_mixer_of_get_id(dev->of_node);
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mixer->cfg = of_device_get_match_data(dev);
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if (!mixer->cfg)
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return -EINVAL;
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regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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mixer->engine.regs = devm_regmap_init_mmio(dev, regs,
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&sun8i_mixer_regmap_config);
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if (IS_ERR(mixer->engine.regs)) {
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dev_err(dev, "Couldn't create the mixer regmap\n");
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return PTR_ERR(mixer->engine.regs);
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}
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mixer->reset = devm_reset_control_get(dev, NULL);
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if (IS_ERR(mixer->reset)) {
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dev_err(dev, "Couldn't get our reset line\n");
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return PTR_ERR(mixer->reset);
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}
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ret = reset_control_deassert(mixer->reset);
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if (ret) {
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dev_err(dev, "Couldn't deassert our reset line\n");
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return ret;
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}
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mixer->bus_clk = devm_clk_get(dev, "bus");
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if (IS_ERR(mixer->bus_clk)) {
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dev_err(dev, "Couldn't get the mixer bus clock\n");
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ret = PTR_ERR(mixer->bus_clk);
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goto err_assert_reset;
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}
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clk_prepare_enable(mixer->bus_clk);
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mixer->mod_clk = devm_clk_get(dev, "mod");
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if (IS_ERR(mixer->mod_clk)) {
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dev_err(dev, "Couldn't get the mixer module clock\n");
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ret = PTR_ERR(mixer->mod_clk);
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goto err_disable_bus_clk;
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}
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/*
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* It seems that we need to enforce that rate for whatever
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* reason for the mixer to be functional. Make sure it's the
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* case.
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*/
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if (mixer->cfg->mod_rate)
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clk_set_rate(mixer->mod_clk, mixer->cfg->mod_rate);
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clk_prepare_enable(mixer->mod_clk);
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list_add_tail(&mixer->engine.list, &drv->engine_list);
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base = sun8i_blender_base(mixer);
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/* Reset registers and disable unused sub-engines */
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if (mixer->cfg->is_de3) {
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for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4)
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regmap_write(mixer->engine.regs, i, 0);
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regmap_write(mixer->engine.regs, SUN50I_MIXER_FCE_EN, 0);
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regmap_write(mixer->engine.regs, SUN50I_MIXER_PEAK_EN, 0);
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regmap_write(mixer->engine.regs, SUN50I_MIXER_LCTI_EN, 0);
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regmap_write(mixer->engine.regs, SUN50I_MIXER_BLS_EN, 0);
|
|
regmap_write(mixer->engine.regs, SUN50I_MIXER_FCC_EN, 0);
|
|
regmap_write(mixer->engine.regs, SUN50I_MIXER_DNS_EN, 0);
|
|
regmap_write(mixer->engine.regs, SUN50I_MIXER_DRC_EN, 0);
|
|
regmap_write(mixer->engine.regs, SUN50I_MIXER_FMT_EN, 0);
|
|
regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC0_EN, 0);
|
|
regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC1_EN, 0);
|
|
} else {
|
|
for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4)
|
|
regmap_write(mixer->engine.regs, i, 0);
|
|
|
|
regmap_write(mixer->engine.regs, SUN8I_MIXER_FCE_EN, 0);
|
|
regmap_write(mixer->engine.regs, SUN8I_MIXER_BWS_EN, 0);
|
|
regmap_write(mixer->engine.regs, SUN8I_MIXER_LTI_EN, 0);
|
|
regmap_write(mixer->engine.regs, SUN8I_MIXER_PEAK_EN, 0);
|
|
regmap_write(mixer->engine.regs, SUN8I_MIXER_ASE_EN, 0);
|
|
regmap_write(mixer->engine.regs, SUN8I_MIXER_FCC_EN, 0);
|
|
regmap_write(mixer->engine.regs, SUN8I_MIXER_DCSC_EN, 0);
|
|
}
|
|
|
|
/* Enable the mixer */
|
|
regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
|
|
SUN8I_MIXER_GLOBAL_CTL_RT_EN);
|
|
|
|
/* Set background color to black */
|
|
regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
|
|
SUN8I_MIXER_BLEND_COLOR_BLACK);
|
|
|
|
/*
|
|
* Set fill color of bottom plane to black. Generally not needed
|
|
* except when VI plane is at bottom (zpos = 0) and enabled.
|
|
*/
|
|
regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
|
|
SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
|
|
regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
|
|
SUN8I_MIXER_BLEND_COLOR_BLACK);
|
|
|
|
plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
|
|
for (i = 0; i < plane_cnt; i++)
|
|
regmap_write(mixer->engine.regs,
|
|
SUN8I_MIXER_BLEND_MODE(base, i),
|
|
SUN8I_MIXER_BLEND_MODE_DEF);
|
|
|
|
regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
|
|
SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
|
|
|
|
return 0;
|
|
|
|
err_disable_bus_clk:
|
|
clk_disable_unprepare(mixer->bus_clk);
|
|
err_assert_reset:
|
|
reset_control_assert(mixer->reset);
|
|
return ret;
|
|
}
|
|
|
|
static void sun8i_mixer_unbind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct sun8i_mixer *mixer = dev_get_drvdata(dev);
|
|
|
|
list_del(&mixer->engine.list);
|
|
|
|
clk_disable_unprepare(mixer->mod_clk);
|
|
clk_disable_unprepare(mixer->bus_clk);
|
|
reset_control_assert(mixer->reset);
|
|
}
|
|
|
|
static const struct component_ops sun8i_mixer_ops = {
|
|
.bind = sun8i_mixer_bind,
|
|
.unbind = sun8i_mixer_unbind,
|
|
};
|
|
|
|
static int sun8i_mixer_probe(struct platform_device *pdev)
|
|
{
|
|
return component_add(&pdev->dev, &sun8i_mixer_ops);
|
|
}
|
|
|
|
static int sun8i_mixer_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &sun8i_mixer_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {
|
|
.ccsc = CCSC_MIXER0_LAYOUT,
|
|
.scaler_mask = 0xf,
|
|
.scanline_yuv = 2048,
|
|
.ui_num = 3,
|
|
.vi_num = 1,
|
|
};
|
|
|
|
static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {
|
|
.ccsc = CCSC_MIXER1_LAYOUT,
|
|
.scaler_mask = 0x3,
|
|
.scanline_yuv = 2048,
|
|
.ui_num = 1,
|
|
.vi_num = 1,
|
|
};
|
|
|
|
static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
|
|
.ccsc = CCSC_MIXER0_LAYOUT,
|
|
.mod_rate = 432000000,
|
|
.scaler_mask = 0xf,
|
|
.scanline_yuv = 2048,
|
|
.ui_num = 3,
|
|
.vi_num = 1,
|
|
};
|
|
|
|
static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
|
|
.ccsc = CCSC_MIXER0_LAYOUT,
|
|
.mod_rate = 297000000,
|
|
.scaler_mask = 0xf,
|
|
.scanline_yuv = 2048,
|
|
.ui_num = 3,
|
|
.vi_num = 1,
|
|
};
|
|
|
|
static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
|
|
.ccsc = CCSC_MIXER1_LAYOUT,
|
|
.mod_rate = 297000000,
|
|
.scaler_mask = 0x3,
|
|
.scanline_yuv = 2048,
|
|
.ui_num = 1,
|
|
.vi_num = 1,
|
|
};
|
|
|
|
static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
|
|
.vi_num = 2,
|
|
.ui_num = 1,
|
|
.scaler_mask = 0x3,
|
|
.scanline_yuv = 2048,
|
|
.ccsc = CCSC_MIXER0_LAYOUT,
|
|
.mod_rate = 150000000,
|
|
};
|
|
|
|
static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = {
|
|
.ccsc = CCSC_D1_MIXER0_LAYOUT,
|
|
.mod_rate = 297000000,
|
|
.scaler_mask = 0x3,
|
|
.scanline_yuv = 2048,
|
|
.ui_num = 1,
|
|
.vi_num = 1,
|
|
};
|
|
|
|
static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = {
|
|
.ccsc = CCSC_MIXER1_LAYOUT,
|
|
.mod_rate = 297000000,
|
|
.scaler_mask = 0x1,
|
|
.scanline_yuv = 1024,
|
|
.ui_num = 0,
|
|
.vi_num = 1,
|
|
};
|
|
|
|
static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = {
|
|
.ccsc = CCSC_MIXER0_LAYOUT,
|
|
.mod_rate = 297000000,
|
|
.scaler_mask = 0xf,
|
|
.scanline_yuv = 4096,
|
|
.ui_num = 3,
|
|
.vi_num = 1,
|
|
};
|
|
|
|
static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
|
|
.ccsc = CCSC_MIXER1_LAYOUT,
|
|
.mod_rate = 297000000,
|
|
.scaler_mask = 0x3,
|
|
.scanline_yuv = 2048,
|
|
.ui_num = 1,
|
|
.vi_num = 1,
|
|
};
|
|
|
|
static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
|
|
.ccsc = CCSC_MIXER0_LAYOUT,
|
|
.is_de3 = true,
|
|
.mod_rate = 600000000,
|
|
.scaler_mask = 0xf,
|
|
.scanline_yuv = 4096,
|
|
.ui_num = 3,
|
|
.vi_num = 1,
|
|
};
|
|
|
|
static const struct of_device_id sun8i_mixer_of_table[] = {
|
|
{
|
|
.compatible = "allwinner,sun8i-a83t-de2-mixer-0",
|
|
.data = &sun8i_a83t_mixer0_cfg,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun8i-a83t-de2-mixer-1",
|
|
.data = &sun8i_a83t_mixer1_cfg,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun8i-h3-de2-mixer-0",
|
|
.data = &sun8i_h3_mixer0_cfg,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun8i-r40-de2-mixer-0",
|
|
.data = &sun8i_r40_mixer0_cfg,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun8i-r40-de2-mixer-1",
|
|
.data = &sun8i_r40_mixer1_cfg,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun8i-v3s-de2-mixer",
|
|
.data = &sun8i_v3s_mixer_cfg,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun20i-d1-de2-mixer-0",
|
|
.data = &sun20i_d1_mixer0_cfg,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun20i-d1-de2-mixer-1",
|
|
.data = &sun20i_d1_mixer1_cfg,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun50i-a64-de2-mixer-0",
|
|
.data = &sun50i_a64_mixer0_cfg,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun50i-a64-de2-mixer-1",
|
|
.data = &sun50i_a64_mixer1_cfg,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun50i-h6-de3-mixer-0",
|
|
.data = &sun50i_h6_mixer0_cfg,
|
|
},
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
|
|
|
|
static struct platform_driver sun8i_mixer_platform_driver = {
|
|
.probe = sun8i_mixer_probe,
|
|
.remove = sun8i_mixer_remove,
|
|
.driver = {
|
|
.name = "sun8i-mixer",
|
|
.of_match_table = sun8i_mixer_of_table,
|
|
},
|
|
};
|
|
module_platform_driver(sun8i_mixer_platform_driver);
|
|
|
|
MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
|
|
MODULE_DESCRIPTION("Allwinner DE2 Mixer driver");
|
|
MODULE_LICENSE("GPL");
|