301 lines
6.3 KiB
C
301 lines
6.3 KiB
C
/*
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* Helper routines for R-Car sound ADG.
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*
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* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/sh_clk.h>
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#include "rsnd.h"
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#define CLKA 0
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#define CLKB 1
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#define CLKC 2
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#define CLKI 3
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#define CLKMAX 4
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struct rsnd_adg {
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struct clk *clk[CLKMAX];
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int rbga_rate_for_441khz_div_6; /* RBGA */
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int rbgb_rate_for_48khz_div_6; /* RBGB */
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u32 ckr;
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};
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#define for_each_rsnd_clk(pos, adg, i) \
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for (i = 0, (pos) = adg->clk[i]; \
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i < CLKMAX; \
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i++, (pos) = adg->clk[i])
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#define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
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static int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
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struct rsnd_mod *mod,
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unsigned int src_rate,
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unsigned int dst_rate)
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{
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct device *dev = rsnd_priv_to_dev(priv);
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int idx, sel, div, shift;
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u32 mask, val;
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int id = rsnd_mod_id(mod);
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unsigned int sel_rate [] = {
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clk_get_rate(adg->clk[CLKA]), /* 000: CLKA */
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clk_get_rate(adg->clk[CLKB]), /* 001: CLKB */
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clk_get_rate(adg->clk[CLKC]), /* 010: CLKC */
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0, /* 011: MLBCLK (not used) */
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adg->rbga_rate_for_441khz_div_6,/* 100: RBGA */
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adg->rbgb_rate_for_48khz_div_6, /* 101: RBGB */
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};
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/* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */
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for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
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for (div = 128, idx = 0;
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div <= 2048;
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div *= 2, idx++) {
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if (src_rate == sel_rate[sel] / div) {
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val = (idx << 4) | sel;
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goto find_rate;
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}
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}
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}
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dev_err(dev, "can't find convert src clk\n");
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return -EINVAL;
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find_rate:
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shift = (id % 4) * 8;
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mask = 0xFF << shift;
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val = val << shift;
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dev_dbg(dev, "adg convert src clk = %02x\n", val);
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switch (id / 4) {
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case 0:
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rsnd_mod_bset(mod, AUDIO_CLK_SEL3, mask, val);
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break;
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case 1:
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rsnd_mod_bset(mod, AUDIO_CLK_SEL4, mask, val);
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break;
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case 2:
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rsnd_mod_bset(mod, AUDIO_CLK_SEL5, mask, val);
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break;
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}
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/*
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* Gen1 doesn't need dst_rate settings,
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* since it uses SSI WS pin.
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* see also rsnd_src_set_route_if_gen1()
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*/
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return 0;
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}
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int rsnd_adg_set_convert_clk(struct rsnd_priv *priv,
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struct rsnd_mod *mod,
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unsigned int src_rate,
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unsigned int dst_rate)
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{
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if (rsnd_is_gen1(priv))
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return rsnd_adg_set_convert_clk_gen1(priv, mod,
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src_rate, dst_rate);
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return -EINVAL;
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}
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static void rsnd_adg_set_ssi_clk(struct rsnd_mod *mod, u32 val)
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{
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int id = rsnd_mod_id(mod);
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int shift = (id % 4) * 8;
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u32 mask = 0xFF << shift;
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val = val << shift;
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/*
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* SSI 8 is not connected to ADG.
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* it works with SSI 7
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*/
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if (id == 8)
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return;
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switch (id / 4) {
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case 0:
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rsnd_mod_bset(mod, AUDIO_CLK_SEL0, mask, val);
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break;
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case 1:
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rsnd_mod_bset(mod, AUDIO_CLK_SEL1, mask, val);
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break;
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case 2:
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rsnd_mod_bset(mod, AUDIO_CLK_SEL2, mask, val);
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break;
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}
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}
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int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
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{
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/*
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* "mod" = "ssi" here.
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* we can get "ssi id" from mod
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*/
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rsnd_adg_set_ssi_clk(mod, 0);
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return 0;
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}
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int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
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{
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struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
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struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
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struct device *dev = rsnd_priv_to_dev(priv);
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struct clk *clk;
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int i;
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u32 data;
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int sel_table[] = {
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[CLKA] = 0x1,
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[CLKB] = 0x2,
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[CLKC] = 0x3,
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[CLKI] = 0x0,
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};
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dev_dbg(dev, "request clock = %d\n", rate);
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/*
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* find suitable clock from
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* AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
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*/
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data = 0;
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for_each_rsnd_clk(clk, adg, i) {
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if (rate == clk_get_rate(clk)) {
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data = sel_table[i];
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goto found_clock;
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}
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}
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/*
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* find 1/6 clock from BRGA/BRGB
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*/
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if (rate == adg->rbga_rate_for_441khz_div_6) {
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data = 0x10;
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goto found_clock;
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}
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if (rate == adg->rbgb_rate_for_48khz_div_6) {
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data = 0x20;
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goto found_clock;
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}
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return -EIO;
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found_clock:
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/* see rsnd_adg_ssi_clk_init() */
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rsnd_mod_bset(mod, SSICKR, 0x00FF0000, adg->ckr);
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rsnd_mod_write(mod, BRRA, 0x00000002); /* 1/6 */
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rsnd_mod_write(mod, BRRB, 0x00000002); /* 1/6 */
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/*
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* This "mod" = "ssi" here.
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* we can get "ssi id" from mod
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*/
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rsnd_adg_set_ssi_clk(mod, data);
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dev_dbg(dev, "ADG: ssi%d selects clk%d = %d",
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rsnd_mod_id(mod), i, rate);
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return 0;
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}
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static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
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{
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struct clk *clk;
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unsigned long rate;
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u32 ckr;
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int i;
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int brg_table[] = {
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[CLKA] = 0x0,
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[CLKB] = 0x1,
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[CLKC] = 0x4,
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[CLKI] = 0x2,
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};
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/*
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* This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
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* have 44.1kHz or 48kHz base clocks for now.
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*
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* SSI itself can divide parent clock by 1/1 - 1/16
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* So, BRGA outputs 44.1kHz base parent clock 1/32,
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* and, BRGB outputs 48.0kHz base parent clock 1/32 here.
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* see
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* rsnd_adg_ssi_clk_try_start()
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*/
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ckr = 0;
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adg->rbga_rate_for_441khz_div_6 = 0;
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adg->rbgb_rate_for_48khz_div_6 = 0;
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for_each_rsnd_clk(clk, adg, i) {
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rate = clk_get_rate(clk);
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if (0 == rate) /* not used */
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continue;
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/* RBGA */
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if (!adg->rbga_rate_for_441khz_div_6 && (0 == rate % 44100)) {
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adg->rbga_rate_for_441khz_div_6 = rate / 6;
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ckr |= brg_table[i] << 20;
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}
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/* RBGB */
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if (!adg->rbgb_rate_for_48khz_div_6 && (0 == rate % 48000)) {
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adg->rbgb_rate_for_48khz_div_6 = rate / 6;
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ckr |= brg_table[i] << 16;
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}
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}
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adg->ckr = ckr;
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}
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int rsnd_adg_probe(struct platform_device *pdev,
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struct rcar_snd_info *info,
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struct rsnd_priv *priv)
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{
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struct rsnd_adg *adg;
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struct device *dev = rsnd_priv_to_dev(priv);
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struct clk *clk;
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int i;
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adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
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if (!adg) {
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dev_err(dev, "ADG allocate failed\n");
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return -ENOMEM;
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}
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adg->clk[CLKA] = clk_get(NULL, "audio_clk_a");
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adg->clk[CLKB] = clk_get(NULL, "audio_clk_b");
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adg->clk[CLKC] = clk_get(NULL, "audio_clk_c");
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adg->clk[CLKI] = clk_get(NULL, "audio_clk_internal");
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for_each_rsnd_clk(clk, adg, i) {
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if (IS_ERR(clk)) {
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dev_err(dev, "Audio clock failed\n");
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return -EIO;
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}
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}
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rsnd_adg_ssi_clk_init(priv, adg);
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priv->adg = adg;
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dev_dbg(dev, "adg probed\n");
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return 0;
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}
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void rsnd_adg_remove(struct platform_device *pdev,
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struct rsnd_priv *priv)
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{
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struct rsnd_adg *adg = priv->adg;
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struct clk *clk;
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int i;
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for_each_rsnd_clk(clk, adg, i)
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clk_put(clk);
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}
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