274 lines
6.5 KiB
C
274 lines
6.5 KiB
C
/*
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* Copyright 2011 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Alex Deucher
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*/
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#include <linux/firmware.h>
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#include "amdgpu.h"
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#include "sid.h"
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#include "ppsmc.h"
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#include "amdgpu_ucode.h"
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#include "sislands_smc.h"
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static int si_set_smc_sram_address(struct amdgpu_device *adev,
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u32 smc_address, u32 limit)
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{
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if (smc_address & 3)
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return -EINVAL;
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if ((smc_address + 3) > limit)
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return -EINVAL;
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WREG32(SMC_IND_INDEX_0, smc_address);
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WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
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return 0;
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}
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int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev,
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u32 smc_start_address,
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const u8 *src, u32 byte_count, u32 limit)
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{
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unsigned long flags;
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int ret = 0;
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u32 data, original_data, addr, extra_shift;
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if (smc_start_address & 3)
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return -EINVAL;
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if ((smc_start_address + byte_count) > limit)
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return -EINVAL;
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addr = smc_start_address;
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spin_lock_irqsave(&adev->smc_idx_lock, flags);
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while (byte_count >= 4) {
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/* SMC address space is BE */
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data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
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ret = si_set_smc_sram_address(adev, addr, limit);
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if (ret)
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goto done;
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WREG32(SMC_IND_DATA_0, data);
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src += 4;
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byte_count -= 4;
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addr += 4;
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}
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/* RMW for the final bytes */
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if (byte_count > 0) {
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data = 0;
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ret = si_set_smc_sram_address(adev, addr, limit);
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if (ret)
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goto done;
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original_data = RREG32(SMC_IND_DATA_0);
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extra_shift = 8 * (4 - byte_count);
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while (byte_count > 0) {
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/* SMC address space is BE */
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data = (data << 8) + *src++;
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byte_count--;
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}
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data <<= extra_shift;
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data |= (original_data & ~((~0UL) << extra_shift));
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ret = si_set_smc_sram_address(adev, addr, limit);
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if (ret)
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goto done;
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WREG32(SMC_IND_DATA_0, data);
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}
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done:
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spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
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return ret;
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}
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void amdgpu_si_start_smc(struct amdgpu_device *adev)
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{
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u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
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tmp &= ~RST_REG;
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WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
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}
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void amdgpu_si_reset_smc(struct amdgpu_device *adev)
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{
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u32 tmp;
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RREG32(CB_CGTT_SCLK_CTRL);
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RREG32(CB_CGTT_SCLK_CTRL);
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RREG32(CB_CGTT_SCLK_CTRL);
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RREG32(CB_CGTT_SCLK_CTRL);
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tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) |
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RST_REG;
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WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp);
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}
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int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev)
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{
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static const u8 data[] = { 0x0E, 0x00, 0x40, 0x40 };
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return amdgpu_si_copy_bytes_to_smc(adev, 0x0, data, 4, sizeof(data)+1);
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}
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void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable)
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{
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u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
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if (enable)
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tmp &= ~CK_DISABLE;
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else
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tmp |= CK_DISABLE;
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WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp);
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}
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bool amdgpu_si_is_smc_running(struct amdgpu_device *adev)
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{
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u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL);
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u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
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if (!(rst & RST_REG) && !(clk & CK_DISABLE))
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return true;
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return false;
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}
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PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev,
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PPSMC_Msg msg)
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{
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u32 tmp;
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int i;
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if (!amdgpu_si_is_smc_running(adev))
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return PPSMC_Result_Failed;
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WREG32(SMC_MESSAGE_0, msg);
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32(SMC_RESP_0);
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if (tmp != 0)
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break;
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udelay(1);
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}
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return (PPSMC_Result)RREG32(SMC_RESP_0);
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}
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PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev)
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{
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u32 tmp;
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int i;
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if (!amdgpu_si_is_smc_running(adev))
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return PPSMC_Result_OK;
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for (i = 0; i < adev->usec_timeout; i++) {
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tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
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if ((tmp & CKEN) == 0)
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break;
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udelay(1);
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}
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return PPSMC_Result_OK;
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}
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int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit)
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{
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const struct smc_firmware_header_v1_0 *hdr;
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unsigned long flags;
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u32 ucode_start_address;
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u32 ucode_size;
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const u8 *src;
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u32 data;
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if (!adev->pm.fw)
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return -EINVAL;
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hdr = (const struct smc_firmware_header_v1_0 *)adev->pm.fw->data;
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amdgpu_ucode_print_smc_hdr(&hdr->header);
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adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
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ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
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ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
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src = (const u8 *)
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(adev->pm.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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if (ucode_size & 3)
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return -EINVAL;
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spin_lock_irqsave(&adev->smc_idx_lock, flags);
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WREG32(SMC_IND_INDEX_0, ucode_start_address);
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WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0);
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while (ucode_size >= 4) {
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/* SMC address space is BE */
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data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3];
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WREG32(SMC_IND_DATA_0, data);
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src += 4;
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ucode_size -= 4;
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}
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WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
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spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
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return 0;
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}
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int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
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u32 *value, u32 limit)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&adev->smc_idx_lock, flags);
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ret = si_set_smc_sram_address(adev, smc_address, limit);
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if (ret == 0)
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*value = RREG32(SMC_IND_DATA_0);
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spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
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return ret;
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}
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int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address,
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u32 value, u32 limit)
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{
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&adev->smc_idx_lock, flags);
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ret = si_set_smc_sram_address(adev, smc_address, limit);
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if (ret == 0)
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WREG32(SMC_IND_DATA_0, value);
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spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
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return ret;
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}
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