231 lines
8.1 KiB
Plaintext
231 lines
8.1 KiB
Plaintext
Common bindings for video receiver and transmitter interfaces
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General concept
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---------------
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Video data pipelines usually consist of external devices, e.g. camera sensors,
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controlled over an I2C, SPI or UART bus, and SoC internal IP blocks, including
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video DMA engines and video data processors.
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SoC internal blocks are described by DT nodes, placed similarly to other SoC
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blocks. External devices are represented as child nodes of their respective
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bus controller nodes, e.g. I2C.
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Data interfaces on all video devices are described by their child 'port' nodes.
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Configuration of a port depends on other devices participating in the data
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transfer and is described by 'endpoint' subnodes.
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device {
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...
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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...
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endpoint@0 { ... };
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endpoint@1 { ... };
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};
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port@1 { ... };
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};
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};
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If a port can be configured to work with more than one remote device on the same
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bus, an 'endpoint' child node must be provided for each of them. If more than
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one port is present in a device node or there is more than one endpoint at a
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port, or port node needs to be associated with a selected hardware interface,
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a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
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used.
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All 'port' nodes can be grouped under optional 'ports' node, which allows to
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specify #address-cells, #size-cells properties independently for the 'port'
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and 'endpoint' nodes and any child device nodes a device might have.
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Two 'endpoint' nodes are linked with each other through their 'remote-endpoint'
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phandles. An endpoint subnode of a device contains all properties needed for
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configuration of this device for data exchange with other device. In most
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cases properties at the peer 'endpoint' nodes will be identical, however they
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might need to be different when there is any signal modifications on the bus
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between two devices, e.g. there are logic signal inverters on the lines.
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It is allowed for multiple endpoints at a port to be active simultaneously,
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where supported by a device. For example, in case where a data interface of
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a device is partitioned into multiple data busses, e.g. 16-bit input port
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divided into two separate ITU-R BT.656 8-bit busses. In such case bus-width
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and data-shift properties can be used to assign physical data lines to each
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endpoint node (logical bus).
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Required properties
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-------------------
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If there is more than one 'port' or more than one 'endpoint' node or 'reg'
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property is present in port and/or endpoint nodes the following properties
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are required in a relevant parent node:
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- #address-cells : number of cells required to define port/endpoint
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identifier, should be 1.
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- #size-cells : should be zero.
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Optional endpoint properties
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----------------------------
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- remote-endpoint: phandle to an 'endpoint' subnode of a remote device node.
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- slave-mode: a boolean property indicating that the link is run in slave mode.
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The default when this property is not specified is master mode. In the slave
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mode horizontal and vertical synchronization signals are provided to the
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slave device (data source) by the master device (data sink). In the master
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mode the data source device is also the source of the synchronization signals.
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- bus-width: number of data lines actively used, valid for the parallel busses.
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- data-shift: on the parallel data busses, if bus-width is used to specify the
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number of data lines, data-shift can be used to specify which data lines are
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used, e.g. "bus-width=<8>; data-shift=<2>;" means, that lines 9:2 are used.
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- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
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- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
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Note, that if HSYNC and VSYNC polarities are not specified, embedded
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synchronization may be required, where supported.
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- data-active: similar to HSYNC and VSYNC, specifies data line polarity.
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- field-even-active: field signal level during the even field data transmission.
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- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock
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signal.
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- sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for
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LOW/HIGH respectively.
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- data-lanes: an array of physical data lane indexes. Position of an entry
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determines the logical lane number, while the value of an entry indicates
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physical lane, e.g. for 2-lane MIPI CSI-2 bus we could have
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"data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0.
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This property is valid for serial busses only (e.g. MIPI CSI-2).
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- clock-lanes: an array of physical clock lane indexes. Position of an entry
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determines the logical lane number, while the value of an entry indicates
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physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;",
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which places the clock lane on hardware lane 0. This property is valid for
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serial busses only (e.g. MIPI CSI-2). Note that for the MIPI CSI-2 bus this
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array contains only one entry.
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- clock-noncontinuous: a boolean property to allow MIPI CSI-2 non-continuous
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clock mode.
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Example
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-------
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The example snippet below describes two data pipelines. ov772x and imx074 are
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camera sensors with a parallel and serial (MIPI CSI-2) video bus respectively.
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Both sensors are on the I2C control bus corresponding to the i2c0 controller
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node. ov772x sensor is linked directly to the ceu0 video host interface.
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imx074 is linked to ceu0 through the MIPI CSI-2 receiver (csi2). ceu0 has a
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(single) DMA engine writing captured data to memory. ceu0 node has a single
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'port' node which may indicate that at any time only one of the following data
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pipelines can be active: ov772x -> ceu0 or imx074 -> csi2 -> ceu0.
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ceu0: ceu@0xfe910000 {
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compatible = "renesas,sh-mobile-ceu";
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reg = <0xfe910000 0xa0>;
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interrupts = <0x880>;
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mclk: master_clock {
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compatible = "renesas,ceu-clock";
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#clock-cells = <1>;
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clock-frequency = <50000000>; /* Max clock frequency */
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clock-output-names = "mclk";
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};
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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/* Parallel bus endpoint */
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ceu0_1: endpoint@1 {
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reg = <1>; /* Local endpoint # */
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remote = <&ov772x_1_1>; /* Remote phandle */
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bus-width = <8>; /* Used data lines */
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data-shift = <2>; /* Lines 9:2 are used */
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/* If hsync-active/vsync-active are missing,
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embedded BT.656 sync is used */
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hsync-active = <0>; /* Active low */
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vsync-active = <0>; /* Active low */
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data-active = <1>; /* Active high */
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pclk-sample = <1>; /* Rising */
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};
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/* MIPI CSI-2 bus endpoint */
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ceu0_0: endpoint@0 {
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reg = <0>;
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remote = <&csi2_2>;
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};
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};
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};
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i2c0: i2c@0xfff20000 {
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...
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ov772x_1: camera@0x21 {
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compatible = "omnivision,ov772x";
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reg = <0x21>;
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vddio-supply = <®ulator1>;
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vddcore-supply = <®ulator2>;
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clock-frequency = <20000000>;
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clocks = <&mclk 0>;
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clock-names = "xclk";
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port {
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/* With 1 endpoint per port no need for addresses. */
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ov772x_1_1: endpoint {
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bus-width = <8>;
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remote-endpoint = <&ceu0_1>;
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hsync-active = <1>;
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vsync-active = <0>; /* Who came up with an
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inverter here ?... */
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data-active = <1>;
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pclk-sample = <1>;
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};
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};
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};
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imx074: camera@0x1a {
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compatible = "sony,imx074";
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reg = <0x1a>;
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vddio-supply = <®ulator1>;
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vddcore-supply = <®ulator2>;
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clock-frequency = <30000000>; /* Shared clock with ov772x_1 */
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clocks = <&mclk 0>;
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clock-names = "sysclk"; /* Assuming this is the
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name in the datasheet */
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port {
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imx074_1: endpoint {
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clock-lanes = <0>;
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data-lanes = <1 2>;
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remote-endpoint = <&csi2_1>;
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};
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};
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};
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};
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csi2: csi2@0xffc90000 {
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compatible = "renesas,sh-mobile-csi2";
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reg = <0xffc90000 0x1000>;
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interrupts = <0x17a0>;
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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compatible = "renesas,csi2c"; /* One of CSI2I and CSI2C. */
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reg = <1>; /* CSI-2 PHY #1 of 2: PHY_S,
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PHY_M has port address 0,
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is unused. */
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csi2_1: endpoint {
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clock-lanes = <0>;
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data-lanes = <2 1>;
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remote-endpoint = <&imx074_1>;
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};
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};
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port@2 {
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reg = <2>; /* port 2: link to the CEU */
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csi2_2: endpoint {
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remote-endpoint = <&ceu0_0>;
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};
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};
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};
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