280 lines
7.0 KiB
C
280 lines
7.0 KiB
C
#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/smp.h>
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#include <linux/kernel_stat.h>
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#include <linux/mc146818rtc.h>
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#include <linux/interrupt.h>
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#include <asm/mtrr.h>
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu_context.h>
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#include <asm/proto.h>
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#include <asm/apicdef.h>
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#include <asm/idle.h>
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#include <asm/uv/uv_hub.h>
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#include <asm/uv/uv_bau.h>
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#include <mach_ipi.h>
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/*
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* Smarter SMP flushing macros.
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* c/o Linus Torvalds.
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*
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* These mean you can really definitely utterly forget about
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* writing to user space from interrupts. (Its not allowed anyway).
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*
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* Optimizations Manfred Spraul <manfred@colorfullife.com>
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*
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* More scalable flush, from Andi Kleen
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*
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* To avoid global state use 8 different call vectors.
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* Each CPU uses a specific vector to trigger flushes on other
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* CPUs. Depending on the received vector the target CPUs look into
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* the right per cpu variable for the flush data.
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*
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* With more than 8 CPUs they are hashed to the 8 available
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* vectors. The limited global vector space forces us to this right now.
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* In future when interrupts are split into per CPU domains this could be
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* fixed, at the cost of triggering multiple IPIs in some cases.
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*/
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union smp_flush_state {
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struct {
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cpumask_t flush_cpumask;
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struct mm_struct *flush_mm;
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unsigned long flush_va;
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spinlock_t tlbstate_lock;
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};
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char pad[SMP_CACHE_BYTES];
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} ____cacheline_aligned;
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/* State is put into the per CPU data section, but padded
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to a full cache line because other CPUs can access it and we don't
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want false sharing in the per cpu data segment. */
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static DEFINE_PER_CPU(union smp_flush_state, flush_state);
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/*
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* We cannot call mmdrop() because we are in interrupt context,
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* instead update mm->cpu_vm_mask.
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*/
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void leave_mm(int cpu)
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{
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if (read_pda(mmu_state) == TLBSTATE_OK)
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BUG();
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cpu_clear(cpu, read_pda(active_mm)->cpu_vm_mask);
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load_cr3(swapper_pg_dir);
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}
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EXPORT_SYMBOL_GPL(leave_mm);
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/*
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*
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* The flush IPI assumes that a thread switch happens in this order:
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* [cpu0: the cpu that switches]
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* 1) switch_mm() either 1a) or 1b)
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* 1a) thread switch to a different mm
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* 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
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* Stop ipi delivery for the old mm. This is not synchronized with
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* the other cpus, but smp_invalidate_interrupt ignore flush ipis
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* for the wrong mm, and in the worst case we perform a superfluous
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* tlb flush.
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* 1a2) set cpu mmu_state to TLBSTATE_OK
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* Now the smp_invalidate_interrupt won't call leave_mm if cpu0
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* was in lazy tlb mode.
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* 1a3) update cpu active_mm
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* Now cpu0 accepts tlb flushes for the new mm.
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* 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
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* Now the other cpus will send tlb flush ipis.
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* 1a4) change cr3.
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* 1b) thread switch without mm change
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* cpu active_mm is correct, cpu0 already handles
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* flush ipis.
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* 1b1) set cpu mmu_state to TLBSTATE_OK
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* 1b2) test_and_set the cpu bit in cpu_vm_mask.
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* Atomically set the bit [other cpus will start sending flush ipis],
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* and test the bit.
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* 1b3) if the bit was 0: leave_mm was called, flush the tlb.
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* 2) switch %%esp, ie current
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*
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* The interrupt must handle 2 special cases:
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* - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
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* - the cpu performs speculative tlb reads, i.e. even if the cpu only
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* runs in kernel space, the cpu could load tlb entries for user space
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* pages.
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*
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* The good news is that cpu mmu_state is local to each cpu, no
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* write/read ordering problems.
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*/
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/*
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* TLB flush IPI:
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*
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* 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
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* 2) Leave the mm if we are in the lazy tlb mode.
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*
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* Interrupts are disabled.
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*/
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asmlinkage void smp_invalidate_interrupt(struct pt_regs *regs)
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{
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int cpu;
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int sender;
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union smp_flush_state *f;
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cpu = smp_processor_id();
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/*
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* orig_rax contains the negated interrupt vector.
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* Use that to determine where the sender put the data.
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*/
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sender = ~regs->orig_ax - INVALIDATE_TLB_VECTOR_START;
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f = &per_cpu(flush_state, sender);
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if (!cpu_isset(cpu, f->flush_cpumask))
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goto out;
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/*
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* This was a BUG() but until someone can quote me the
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* line from the intel manual that guarantees an IPI to
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* multiple CPUs is retried _only_ on the erroring CPUs
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* its staying as a return
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*
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* BUG();
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*/
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if (f->flush_mm == read_pda(active_mm)) {
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if (read_pda(mmu_state) == TLBSTATE_OK) {
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if (f->flush_va == TLB_FLUSH_ALL)
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local_flush_tlb();
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else
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__flush_tlb_one(f->flush_va);
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} else
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leave_mm(cpu);
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}
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out:
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ack_APIC_irq();
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cpu_clear(cpu, f->flush_cpumask);
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add_pda(irq_tlb_count, 1);
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}
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void native_flush_tlb_others(const cpumask_t *cpumaskp, struct mm_struct *mm,
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unsigned long va)
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{
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int sender;
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union smp_flush_state *f;
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cpumask_t cpumask = *cpumaskp;
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if (is_uv_system() && uv_flush_tlb_others(&cpumask, mm, va))
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return;
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/* Caller has disabled preemption */
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sender = smp_processor_id() % NUM_INVALIDATE_TLB_VECTORS;
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f = &per_cpu(flush_state, sender);
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/*
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* Could avoid this lock when
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* num_online_cpus() <= NUM_INVALIDATE_TLB_VECTORS, but it is
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* probably not worth checking this for a cache-hot lock.
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*/
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spin_lock(&f->tlbstate_lock);
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f->flush_mm = mm;
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f->flush_va = va;
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cpus_or(f->flush_cpumask, cpumask, f->flush_cpumask);
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/*
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* We have to send the IPI only to
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* CPUs affected.
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*/
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send_IPI_mask(cpumask, INVALIDATE_TLB_VECTOR_START + sender);
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while (!cpus_empty(f->flush_cpumask))
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cpu_relax();
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f->flush_mm = NULL;
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f->flush_va = 0;
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spin_unlock(&f->tlbstate_lock);
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}
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static int __cpuinit init_smp_flush(void)
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{
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int i;
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for_each_possible_cpu(i)
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spin_lock_init(&per_cpu(flush_state, i).tlbstate_lock);
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return 0;
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}
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core_initcall(init_smp_flush);
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void flush_tlb_current_task(void)
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{
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struct mm_struct *mm = current->mm;
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cpumask_t cpu_mask;
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preempt_disable();
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cpu_mask = mm->cpu_vm_mask;
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cpu_clear(smp_processor_id(), cpu_mask);
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local_flush_tlb();
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if (!cpus_empty(cpu_mask))
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flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
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preempt_enable();
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}
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void flush_tlb_mm(struct mm_struct *mm)
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{
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cpumask_t cpu_mask;
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preempt_disable();
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cpu_mask = mm->cpu_vm_mask;
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cpu_clear(smp_processor_id(), cpu_mask);
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if (current->active_mm == mm) {
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if (current->mm)
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local_flush_tlb();
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else
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leave_mm(smp_processor_id());
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}
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if (!cpus_empty(cpu_mask))
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flush_tlb_others(cpu_mask, mm, TLB_FLUSH_ALL);
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preempt_enable();
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
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{
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struct mm_struct *mm = vma->vm_mm;
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cpumask_t cpu_mask;
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preempt_disable();
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cpu_mask = mm->cpu_vm_mask;
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cpu_clear(smp_processor_id(), cpu_mask);
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if (current->active_mm == mm) {
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if (current->mm)
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__flush_tlb_one(va);
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else
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leave_mm(smp_processor_id());
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}
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if (!cpus_empty(cpu_mask))
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flush_tlb_others(cpu_mask, mm, va);
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preempt_enable();
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}
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static void do_flush_tlb_all(void *info)
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{
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unsigned long cpu = smp_processor_id();
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__flush_tlb_all();
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if (read_pda(mmu_state) == TLBSTATE_LAZY)
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leave_mm(cpu);
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}
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void flush_tlb_all(void)
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{
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on_each_cpu(do_flush_tlb_all, NULL, 1);
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}
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