545 lines
13 KiB
C
545 lines
13 KiB
C
/*
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* Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/init.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/regmap.h>
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#include <linux/soc/mediatek/infracfg.h>
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#include <linux/regulator/consumer.h>
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#include <dt-bindings/power/mt8173-power.h>
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#define SPM_VDE_PWR_CON 0x0210
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#define SPM_MFG_PWR_CON 0x0214
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#define SPM_VEN_PWR_CON 0x0230
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#define SPM_ISP_PWR_CON 0x0238
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#define SPM_DIS_PWR_CON 0x023c
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#define SPM_VEN2_PWR_CON 0x0298
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#define SPM_AUDIO_PWR_CON 0x029c
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#define SPM_MFG_2D_PWR_CON 0x02c0
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#define SPM_MFG_ASYNC_PWR_CON 0x02c4
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#define SPM_USB_PWR_CON 0x02cc
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#define SPM_PWR_STATUS 0x060c
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#define SPM_PWR_STATUS_2ND 0x0610
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#define PWR_RST_B_BIT BIT(0)
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#define PWR_ISO_BIT BIT(1)
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#define PWR_ON_BIT BIT(2)
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#define PWR_ON_2ND_BIT BIT(3)
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#define PWR_CLK_DIS_BIT BIT(4)
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#define PWR_STATUS_DISP BIT(3)
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#define PWR_STATUS_MFG BIT(4)
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#define PWR_STATUS_ISP BIT(5)
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#define PWR_STATUS_VDEC BIT(7)
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#define PWR_STATUS_VENC_LT BIT(20)
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#define PWR_STATUS_VENC BIT(21)
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#define PWR_STATUS_MFG_2D BIT(22)
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#define PWR_STATUS_MFG_ASYNC BIT(23)
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#define PWR_STATUS_AUDIO BIT(24)
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#define PWR_STATUS_USB BIT(25)
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enum clk_id {
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MT8173_CLK_NONE,
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MT8173_CLK_MM,
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MT8173_CLK_MFG,
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MT8173_CLK_VENC,
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MT8173_CLK_VENC_LT,
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MT8173_CLK_MAX,
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};
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#define MAX_CLKS 2
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struct scp_domain_data {
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const char *name;
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u32 sta_mask;
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int ctl_offs;
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u32 sram_pdn_bits;
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u32 sram_pdn_ack_bits;
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u32 bus_prot_mask;
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enum clk_id clk_id[MAX_CLKS];
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bool active_wakeup;
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};
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static const struct scp_domain_data scp_domain_data[] = {
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[MT8173_POWER_DOMAIN_VDEC] = {
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.name = "vdec",
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.sta_mask = PWR_STATUS_VDEC,
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.ctl_offs = SPM_VDE_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.clk_id = {MT8173_CLK_MM},
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},
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[MT8173_POWER_DOMAIN_VENC] = {
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.name = "venc",
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.sta_mask = PWR_STATUS_VENC,
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.ctl_offs = SPM_VEN_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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.clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC},
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},
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[MT8173_POWER_DOMAIN_ISP] = {
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.name = "isp",
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.sta_mask = PWR_STATUS_ISP,
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.ctl_offs = SPM_ISP_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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.clk_id = {MT8173_CLK_MM},
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},
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[MT8173_POWER_DOMAIN_MM] = {
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.name = "mm",
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.sta_mask = PWR_STATUS_DISP,
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.ctl_offs = SPM_DIS_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(12, 12),
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.clk_id = {MT8173_CLK_MM},
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.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
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MT8173_TOP_AXI_PROT_EN_MM_M1,
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},
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[MT8173_POWER_DOMAIN_VENC_LT] = {
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.name = "venc_lt",
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.sta_mask = PWR_STATUS_VENC_LT,
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.ctl_offs = SPM_VEN2_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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.clk_id = {MT8173_CLK_MM, MT8173_CLK_VENC_LT},
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},
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[MT8173_POWER_DOMAIN_AUDIO] = {
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.name = "audio",
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.sta_mask = PWR_STATUS_AUDIO,
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.ctl_offs = SPM_AUDIO_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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.clk_id = {MT8173_CLK_NONE},
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},
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[MT8173_POWER_DOMAIN_USB] = {
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.name = "usb",
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.sta_mask = PWR_STATUS_USB,
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.ctl_offs = SPM_USB_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(15, 12),
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.clk_id = {MT8173_CLK_NONE},
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.active_wakeup = true,
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},
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[MT8173_POWER_DOMAIN_MFG_ASYNC] = {
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.name = "mfg_async",
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.sta_mask = PWR_STATUS_MFG_ASYNC,
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.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = 0,
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.clk_id = {MT8173_CLK_MFG},
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},
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[MT8173_POWER_DOMAIN_MFG_2D] = {
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.name = "mfg_2d",
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.sta_mask = PWR_STATUS_MFG_2D,
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.ctl_offs = SPM_MFG_2D_PWR_CON,
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.sram_pdn_bits = GENMASK(11, 8),
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.sram_pdn_ack_bits = GENMASK(13, 12),
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.clk_id = {MT8173_CLK_NONE},
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},
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[MT8173_POWER_DOMAIN_MFG] = {
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.name = "mfg",
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.sta_mask = PWR_STATUS_MFG,
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.ctl_offs = SPM_MFG_PWR_CON,
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.sram_pdn_bits = GENMASK(13, 8),
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.sram_pdn_ack_bits = GENMASK(21, 16),
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.clk_id = {MT8173_CLK_NONE},
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.bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
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MT8173_TOP_AXI_PROT_EN_MFG_M0 |
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MT8173_TOP_AXI_PROT_EN_MFG_M1 |
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MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
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},
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};
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#define NUM_DOMAINS ARRAY_SIZE(scp_domain_data)
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struct scp;
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struct scp_domain {
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struct generic_pm_domain genpd;
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struct scp *scp;
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struct clk *clk[MAX_CLKS];
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const struct scp_domain_data *data;
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struct regulator *supply;
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};
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struct scp {
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struct scp_domain domains[NUM_DOMAINS];
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struct genpd_onecell_data pd_data;
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struct device *dev;
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void __iomem *base;
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struct regmap *infracfg;
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};
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static int scpsys_domain_is_on(struct scp_domain *scpd)
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{
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struct scp *scp = scpd->scp;
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u32 status = readl(scp->base + SPM_PWR_STATUS) & scpd->data->sta_mask;
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u32 status2 = readl(scp->base + SPM_PWR_STATUS_2ND) &
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scpd->data->sta_mask;
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/*
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* A domain is on when both status bits are set. If only one is set
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* return an error. This happens while powering up a domain
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*/
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if (status && status2)
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return true;
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if (!status && !status2)
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return false;
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return -EINVAL;
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}
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static int scpsys_power_on(struct generic_pm_domain *genpd)
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{
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struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
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struct scp *scp = scpd->scp;
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unsigned long timeout;
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bool expired;
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void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
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u32 sram_pdn_ack = scpd->data->sram_pdn_ack_bits;
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u32 val;
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int ret;
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int i;
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if (scpd->supply) {
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ret = regulator_enable(scpd->supply);
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if (ret)
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return ret;
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}
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for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++) {
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ret = clk_prepare_enable(scpd->clk[i]);
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if (ret) {
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for (--i; i >= 0; i--)
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clk_disable_unprepare(scpd->clk[i]);
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goto err_clk;
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}
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}
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val = readl(ctl_addr);
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val |= PWR_ON_BIT;
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writel(val, ctl_addr);
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val |= PWR_ON_2ND_BIT;
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writel(val, ctl_addr);
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/* wait until PWR_ACK = 1 */
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timeout = jiffies + HZ;
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expired = false;
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while (1) {
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ret = scpsys_domain_is_on(scpd);
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if (ret > 0)
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break;
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if (expired) {
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ret = -ETIMEDOUT;
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goto err_pwr_ack;
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}
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cpu_relax();
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if (time_after(jiffies, timeout))
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expired = true;
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}
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val &= ~PWR_CLK_DIS_BIT;
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writel(val, ctl_addr);
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val &= ~PWR_ISO_BIT;
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writel(val, ctl_addr);
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val |= PWR_RST_B_BIT;
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writel(val, ctl_addr);
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val &= ~scpd->data->sram_pdn_bits;
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writel(val, ctl_addr);
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/* wait until SRAM_PDN_ACK all 0 */
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timeout = jiffies + HZ;
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expired = false;
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while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
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if (expired) {
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ret = -ETIMEDOUT;
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goto err_pwr_ack;
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}
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cpu_relax();
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if (time_after(jiffies, timeout))
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expired = true;
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}
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if (scpd->data->bus_prot_mask) {
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ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
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scpd->data->bus_prot_mask);
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if (ret)
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goto err_pwr_ack;
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}
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return 0;
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err_pwr_ack:
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for (i = MAX_CLKS - 1; i >= 0; i--) {
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if (scpd->clk[i])
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clk_disable_unprepare(scpd->clk[i]);
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}
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err_clk:
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if (scpd->supply)
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regulator_disable(scpd->supply);
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dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
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return ret;
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}
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static int scpsys_power_off(struct generic_pm_domain *genpd)
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{
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struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
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struct scp *scp = scpd->scp;
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unsigned long timeout;
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bool expired;
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void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
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u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
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u32 val;
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int ret;
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int i;
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if (scpd->data->bus_prot_mask) {
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ret = mtk_infracfg_set_bus_protection(scp->infracfg,
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scpd->data->bus_prot_mask);
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if (ret)
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goto out;
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}
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val = readl(ctl_addr);
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val |= scpd->data->sram_pdn_bits;
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writel(val, ctl_addr);
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/* wait until SRAM_PDN_ACK all 1 */
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timeout = jiffies + HZ;
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expired = false;
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while (pdn_ack && (readl(ctl_addr) & pdn_ack) != pdn_ack) {
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if (expired) {
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ret = -ETIMEDOUT;
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goto out;
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}
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cpu_relax();
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if (time_after(jiffies, timeout))
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expired = true;
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}
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val |= PWR_ISO_BIT;
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writel(val, ctl_addr);
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val &= ~PWR_RST_B_BIT;
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writel(val, ctl_addr);
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val |= PWR_CLK_DIS_BIT;
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writel(val, ctl_addr);
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val &= ~PWR_ON_BIT;
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writel(val, ctl_addr);
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val &= ~PWR_ON_2ND_BIT;
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writel(val, ctl_addr);
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/* wait until PWR_ACK = 0 */
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timeout = jiffies + HZ;
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expired = false;
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while (1) {
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ret = scpsys_domain_is_on(scpd);
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if (ret == 0)
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break;
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if (expired) {
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ret = -ETIMEDOUT;
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goto out;
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}
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cpu_relax();
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if (time_after(jiffies, timeout))
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expired = true;
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}
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for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++)
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clk_disable_unprepare(scpd->clk[i]);
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if (scpd->supply)
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regulator_disable(scpd->supply);
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return 0;
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out:
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dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);
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return ret;
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}
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static bool scpsys_active_wakeup(struct device *dev)
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{
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struct generic_pm_domain *genpd;
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struct scp_domain *scpd;
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genpd = pd_to_genpd(dev->pm_domain);
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scpd = container_of(genpd, struct scp_domain, genpd);
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return scpd->data->active_wakeup;
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}
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static int scpsys_probe(struct platform_device *pdev)
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{
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struct genpd_onecell_data *pd_data;
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struct resource *res;
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int i, j, ret;
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struct scp *scp;
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struct clk *clk[MT8173_CLK_MAX];
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scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
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if (!scp)
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return -ENOMEM;
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scp->dev = &pdev->dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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scp->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(scp->base))
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return PTR_ERR(scp->base);
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pd_data = &scp->pd_data;
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pd_data->domains = devm_kzalloc(&pdev->dev,
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sizeof(*pd_data->domains) * NUM_DOMAINS, GFP_KERNEL);
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if (!pd_data->domains)
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return -ENOMEM;
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clk[MT8173_CLK_MM] = devm_clk_get(&pdev->dev, "mm");
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if (IS_ERR(clk[MT8173_CLK_MM]))
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return PTR_ERR(clk[MT8173_CLK_MM]);
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clk[MT8173_CLK_MFG] = devm_clk_get(&pdev->dev, "mfg");
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if (IS_ERR(clk[MT8173_CLK_MFG]))
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return PTR_ERR(clk[MT8173_CLK_MFG]);
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clk[MT8173_CLK_VENC] = devm_clk_get(&pdev->dev, "venc");
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if (IS_ERR(clk[MT8173_CLK_VENC]))
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return PTR_ERR(clk[MT8173_CLK_VENC]);
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clk[MT8173_CLK_VENC_LT] = devm_clk_get(&pdev->dev, "venc_lt");
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if (IS_ERR(clk[MT8173_CLK_VENC_LT]))
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return PTR_ERR(clk[MT8173_CLK_VENC_LT]);
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scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"infracfg");
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if (IS_ERR(scp->infracfg)) {
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dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
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PTR_ERR(scp->infracfg));
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return PTR_ERR(scp->infracfg);
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}
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for (i = 0; i < NUM_DOMAINS; i++) {
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struct scp_domain *scpd = &scp->domains[i];
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const struct scp_domain_data *data = &scp_domain_data[i];
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scpd->supply = devm_regulator_get_optional(&pdev->dev, data->name);
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if (IS_ERR(scpd->supply)) {
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if (PTR_ERR(scpd->supply) == -ENODEV)
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scpd->supply = NULL;
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else
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return PTR_ERR(scpd->supply);
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}
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}
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pd_data->num_domains = NUM_DOMAINS;
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for (i = 0; i < NUM_DOMAINS; i++) {
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struct scp_domain *scpd = &scp->domains[i];
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struct generic_pm_domain *genpd = &scpd->genpd;
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const struct scp_domain_data *data = &scp_domain_data[i];
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pd_data->domains[i] = genpd;
|
|
scpd->scp = scp;
|
|
|
|
scpd->data = data;
|
|
for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++)
|
|
scpd->clk[j] = clk[data->clk_id[j]];
|
|
|
|
genpd->name = data->name;
|
|
genpd->power_off = scpsys_power_off;
|
|
genpd->power_on = scpsys_power_on;
|
|
genpd->dev_ops.active_wakeup = scpsys_active_wakeup;
|
|
|
|
/*
|
|
* Initially turn on all domains to make the domains usable
|
|
* with !CONFIG_PM and to get the hardware in sync with the
|
|
* software. The unused domains will be switched off during
|
|
* late_init time.
|
|
*/
|
|
genpd->power_on(genpd);
|
|
|
|
pm_genpd_init(genpd, NULL, false);
|
|
}
|
|
|
|
/*
|
|
* We are not allowed to fail here since there is no way to unregister
|
|
* a power domain. Once registered above we have to keep the domains
|
|
* valid.
|
|
*/
|
|
|
|
ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_ASYNC],
|
|
pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D]);
|
|
if (ret && IS_ENABLED(CONFIG_PM))
|
|
dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
|
|
|
|
ret = pm_genpd_add_subdomain(pd_data->domains[MT8173_POWER_DOMAIN_MFG_2D],
|
|
pd_data->domains[MT8173_POWER_DOMAIN_MFG]);
|
|
if (ret && IS_ENABLED(CONFIG_PM))
|
|
dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
|
|
|
|
ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
|
|
if (ret)
|
|
dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id of_scpsys_match_tbl[] = {
|
|
{
|
|
.compatible = "mediatek,mt8173-scpsys",
|
|
}, {
|
|
/* sentinel */
|
|
}
|
|
};
|
|
|
|
static struct platform_driver scpsys_drv = {
|
|
.probe = scpsys_probe,
|
|
.driver = {
|
|
.name = "mtk-scpsys",
|
|
.suppress_bind_attrs = true,
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = of_match_ptr(of_scpsys_match_tbl),
|
|
},
|
|
};
|
|
builtin_platform_driver(scpsys_drv);
|