73 lines
2.7 KiB
C
73 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2019-2020 ARM Limited or its affiliates. */
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#include <linux/bitops.h>
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#define POWER_DOWN_ENABLE 0x01
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#define POWER_DOWN_DISABLE 0x00
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/* hwrng quality: bits of true entropy per 1024 bits of input */
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#define CC_TRNG_QUALITY 1024
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/* CryptoCell TRNG HW definitions */
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#define CC_TRNG_NUM_OF_ROSCS 4
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/* The number of words generated in the entropy holding register (EHR)
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* 6 words (192 bit) according to HW implementation
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*/
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#define CC_TRNG_EHR_IN_WORDS 6
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#define CC_TRNG_EHR_IN_BITS (CC_TRNG_EHR_IN_WORDS * BITS_PER_TYPE(u32))
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#define CC_HOST_RNG_IRQ_MASK BIT(CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT)
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/* RNG interrupt mask */
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#define CC_RNG_INT_MASK (BIT(CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT) | \
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BIT(CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT) | \
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BIT(CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT) | \
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BIT(CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT) | \
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BIT(CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT))
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// --------------------------------------
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// BLOCK: RNG
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// --------------------------------------
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#define CC_RNG_IMR_REG_OFFSET 0x0100UL
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#define CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT 0x0UL
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#define CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT 0x1UL
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#define CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT 0x2UL
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#define CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT 0x3UL
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#define CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT 0x4UL
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#define CC_RNG_ISR_REG_OFFSET 0x0104UL
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#define CC_RNG_ISR_EHR_VALID_BIT_SHIFT 0x0UL
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#define CC_RNG_ISR_EHR_VALID_BIT_SIZE 0x1UL
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#define CC_RNG_ISR_AUTOCORR_ERR_BIT_SHIFT 0x1UL
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#define CC_RNG_ISR_AUTOCORR_ERR_BIT_SIZE 0x1UL
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#define CC_RNG_ISR_CRNGT_ERR_BIT_SHIFT 0x2UL
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#define CC_RNG_ISR_CRNGT_ERR_BIT_SIZE 0x1UL
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#define CC_RNG_ISR_WATCHDOG_BIT_SHIFT 0x4UL
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#define CC_RNG_ISR_WATCHDOG_BIT_SIZE 0x1UL
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#define CC_RNG_ICR_REG_OFFSET 0x0108UL
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#define CC_TRNG_CONFIG_REG_OFFSET 0x010CUL
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#define CC_EHR_DATA_0_REG_OFFSET 0x0114UL
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#define CC_RND_SOURCE_ENABLE_REG_OFFSET 0x012CUL
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#define CC_SAMPLE_CNT1_REG_OFFSET 0x0130UL
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#define CC_TRNG_DEBUG_CONTROL_REG_OFFSET 0x0138UL
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#define CC_RNG_SW_RESET_REG_OFFSET 0x0140UL
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#define CC_RNG_CLK_ENABLE_REG_OFFSET 0x01C4UL
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#define CC_RNG_DMA_ENABLE_REG_OFFSET 0x01C8UL
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#define CC_RNG_WATCHDOG_VAL_REG_OFFSET 0x01D8UL
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// --------------------------------------
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// BLOCK: SEC_HOST_RGF
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// --------------------------------------
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#define CC_HOST_RGF_IRR_REG_OFFSET 0x0A00UL
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#define CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT 0xAUL
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#define CC_HOST_RGF_IMR_REG_OFFSET 0x0A04UL
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#define CC_HOST_RGF_ICR_REG_OFFSET 0x0A08UL
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#define CC_HOST_POWER_DOWN_EN_REG_OFFSET 0x0A78UL
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// --------------------------------------
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// BLOCK: NVM
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// --------------------------------------
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#define CC_NVM_IS_IDLE_REG_OFFSET 0x0F10UL
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#define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT 0x0UL
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#define CC_NVM_IS_IDLE_VALUE_BIT_SIZE 0x1UL
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