341 lines
8.8 KiB
C
341 lines
8.8 KiB
C
/*
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* Copyright (c) 2010-20122Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS5250 - CPU frequency scaling support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/cpufreq.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/cpufreq.h>
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#define CPUFREQ_LEVEL_END (L15 + 1)
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static int max_support_idx;
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static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
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static struct clk *cpu_clk;
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static struct clk *moutcore;
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static struct clk *mout_mpll;
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static struct clk *mout_apll;
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struct cpufreq_clkdiv {
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unsigned int index;
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unsigned int clkdiv;
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unsigned int clkdiv1;
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};
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static unsigned int exynos5250_volt_table[CPUFREQ_LEVEL_END];
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static struct cpufreq_frequency_table exynos5250_freq_table[] = {
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{L0, 1700 * 1000},
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{L1, 1600 * 1000},
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{L2, 1500 * 1000},
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{L3, 1400 * 1000},
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{L4, 1300 * 1000},
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{L5, 1200 * 1000},
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{L6, 1100 * 1000},
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{L7, 1000 * 1000},
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{L8, 900 * 1000},
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{L9, 800 * 1000},
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{L10, 700 * 1000},
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{L11, 600 * 1000},
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{L12, 500 * 1000},
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{L13, 400 * 1000},
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{L14, 300 * 1000},
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{L15, 200 * 1000},
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{0, CPUFREQ_TABLE_END},
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};
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static struct cpufreq_clkdiv exynos5250_clkdiv_table[CPUFREQ_LEVEL_END];
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static unsigned int clkdiv_cpu0_5250[CPUFREQ_LEVEL_END][8] = {
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/*
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* Clock divider value for following
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* { ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 }
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*/
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{ 0, 3, 7, 7, 7, 3, 5, 0 }, /* 1700 MHz */
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{ 0, 3, 7, 7, 7, 1, 4, 0 }, /* 1600 MHz */
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{ 0, 2, 7, 7, 7, 1, 4, 0 }, /* 1500 MHz */
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{ 0, 2, 7, 7, 6, 1, 4, 0 }, /* 1400 MHz */
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{ 0, 2, 7, 7, 6, 1, 3, 0 }, /* 1300 MHz */
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{ 0, 2, 7, 7, 5, 1, 3, 0 }, /* 1200 MHz */
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{ 0, 3, 7, 7, 5, 1, 3, 0 }, /* 1100 MHz */
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{ 0, 1, 7, 7, 4, 1, 2, 0 }, /* 1000 MHz */
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{ 0, 1, 7, 7, 4, 1, 2, 0 }, /* 900 MHz */
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{ 0, 1, 7, 7, 4, 1, 2, 0 }, /* 800 MHz */
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{ 0, 1, 7, 7, 3, 1, 1, 0 }, /* 700 MHz */
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{ 0, 1, 7, 7, 3, 1, 1, 0 }, /* 600 MHz */
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{ 0, 1, 7, 7, 2, 1, 1, 0 }, /* 500 MHz */
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{ 0, 1, 7, 7, 2, 1, 1, 0 }, /* 400 MHz */
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{ 0, 1, 7, 7, 1, 1, 1, 0 }, /* 300 MHz */
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{ 0, 1, 7, 7, 1, 1, 1, 0 }, /* 200 MHz */
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};
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static unsigned int clkdiv_cpu1_5250[CPUFREQ_LEVEL_END][2] = {
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/* Clock divider value for following
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* { COPY, HPM }
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*/
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{ 0, 2 }, /* 1700 MHz */
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{ 0, 2 }, /* 1600 MHz */
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{ 0, 2 }, /* 1500 MHz */
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{ 0, 2 }, /* 1400 MHz */
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{ 0, 2 }, /* 1300 MHz */
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{ 0, 2 }, /* 1200 MHz */
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{ 0, 2 }, /* 1100 MHz */
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{ 0, 2 }, /* 1000 MHz */
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{ 0, 2 }, /* 900 MHz */
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{ 0, 2 }, /* 800 MHz */
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{ 0, 2 }, /* 700 MHz */
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{ 0, 2 }, /* 600 MHz */
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{ 0, 2 }, /* 500 MHz */
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{ 0, 2 }, /* 400 MHz */
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{ 0, 2 }, /* 300 MHz */
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{ 0, 2 }, /* 200 MHz */
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};
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static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = {
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((425 << 16) | (6 << 8) | 0), /* 1700 MHz */
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((200 << 16) | (3 << 8) | 0), /* 1600 MHz */
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((250 << 16) | (4 << 8) | 0), /* 1500 MHz */
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((175 << 16) | (3 << 8) | 0), /* 1400 MHz */
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((325 << 16) | (6 << 8) | 0), /* 1300 MHz */
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((200 << 16) | (4 << 8) | 0), /* 1200 MHz */
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((275 << 16) | (6 << 8) | 0), /* 1100 MHz */
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((125 << 16) | (3 << 8) | 0), /* 1000 MHz */
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((150 << 16) | (4 << 8) | 0), /* 900 MHz */
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((100 << 16) | (3 << 8) | 0), /* 800 MHz */
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((175 << 16) | (3 << 8) | 1), /* 700 MHz */
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((200 << 16) | (4 << 8) | 1), /* 600 MHz */
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((125 << 16) | (3 << 8) | 1), /* 500 MHz */
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((100 << 16) | (3 << 8) | 1), /* 400 MHz */
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((200 << 16) | (4 << 8) | 2), /* 300 MHz */
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((100 << 16) | (3 << 8) | 2), /* 200 MHz */
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};
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/* ASV group voltage table */
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static const unsigned int asv_voltage_5250[CPUFREQ_LEVEL_END] = {
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1300000, 1250000, 1225000, 1200000, 1150000,
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1125000, 1100000, 1075000, 1050000, 1025000,
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1012500, 1000000, 975000, 950000, 937500,
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925000
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};
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static void set_clkdiv(unsigned int div_index)
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{
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unsigned int tmp;
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/* Change Divider - CPU0 */
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tmp = exynos5250_clkdiv_table[div_index].clkdiv;
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__raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
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while (__raw_readl(EXYNOS5_CLKDIV_STATCPU0) & 0x11111111)
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cpu_relax();
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/* Change Divider - CPU1 */
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tmp = exynos5250_clkdiv_table[div_index].clkdiv1;
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__raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
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while (__raw_readl(EXYNOS5_CLKDIV_STATCPU1) & 0x11)
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cpu_relax();
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}
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static void set_apll(unsigned int new_index,
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unsigned int old_index)
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{
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unsigned int tmp, pdiv;
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/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
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clk_set_parent(moutcore, mout_mpll);
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do {
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cpu_relax();
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tmp = (__raw_readl(EXYNOS5_CLKMUX_STATCPU) >> 16);
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tmp &= 0x7;
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} while (tmp != 0x2);
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/* 2. Set APLL Lock time */
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pdiv = ((exynos5_apll_pms_table[new_index] >> 8) & 0x3f);
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__raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK);
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/* 3. Change PLL PMS values */
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tmp = __raw_readl(EXYNOS5_APLL_CON0);
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tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
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tmp |= exynos5_apll_pms_table[new_index];
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__raw_writel(tmp, EXYNOS5_APLL_CON0);
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/* 4. wait_lock_time */
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do {
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cpu_relax();
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tmp = __raw_readl(EXYNOS5_APLL_CON0);
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} while (!(tmp & (0x1 << 29)));
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/* 5. MUX_CORE_SEL = APLL */
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clk_set_parent(moutcore, mout_apll);
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do {
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cpu_relax();
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tmp = __raw_readl(EXYNOS5_CLKMUX_STATCPU);
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tmp &= (0x7 << 16);
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} while (tmp != (0x1 << 16));
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}
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bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index)
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{
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unsigned int old_pm = (exynos5_apll_pms_table[old_index] >> 8);
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unsigned int new_pm = (exynos5_apll_pms_table[new_index] >> 8);
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return (old_pm == new_pm) ? 0 : 1;
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}
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static void exynos5250_set_frequency(unsigned int old_index,
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unsigned int new_index)
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{
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unsigned int tmp;
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if (old_index > new_index) {
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if (!exynos5250_pms_change(old_index, new_index)) {
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/* 1. Change the system clock divider values */
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set_clkdiv(new_index);
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/* 2. Change just s value in apll m,p,s value */
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tmp = __raw_readl(EXYNOS5_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= (exynos5_apll_pms_table[new_index] & 0x7);
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__raw_writel(tmp, EXYNOS5_APLL_CON0);
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} else {
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/* Clock Configuration Procedure */
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/* 1. Change the system clock divider values */
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set_clkdiv(new_index);
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/* 2. Change the apll m,p,s value */
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set_apll(new_index, old_index);
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}
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} else if (old_index < new_index) {
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if (!exynos5250_pms_change(old_index, new_index)) {
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/* 1. Change just s value in apll m,p,s value */
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tmp = __raw_readl(EXYNOS5_APLL_CON0);
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tmp &= ~(0x7 << 0);
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tmp |= (exynos5_apll_pms_table[new_index] & 0x7);
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__raw_writel(tmp, EXYNOS5_APLL_CON0);
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/* 2. Change the system clock divider values */
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set_clkdiv(new_index);
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} else {
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/* Clock Configuration Procedure */
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/* 1. Change the apll m,p,s value */
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set_apll(new_index, old_index);
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/* 2. Change the system clock divider values */
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set_clkdiv(new_index);
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}
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}
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}
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static void __init set_volt_table(void)
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{
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unsigned int i;
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max_support_idx = L0;
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for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
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exynos5250_volt_table[i] = asv_voltage_5250[i];
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}
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int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
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{
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int i;
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unsigned int tmp;
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unsigned long rate;
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set_volt_table();
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cpu_clk = clk_get(NULL, "armclk");
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if (IS_ERR(cpu_clk))
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return PTR_ERR(cpu_clk);
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moutcore = clk_get(NULL, "mout_cpu");
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if (IS_ERR(moutcore))
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goto err_moutcore;
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mout_mpll = clk_get(NULL, "mout_mpll");
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if (IS_ERR(mout_mpll))
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goto err_mout_mpll;
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rate = clk_get_rate(mout_mpll) / 1000;
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mout_apll = clk_get(NULL, "mout_apll");
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if (IS_ERR(mout_apll))
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goto err_mout_apll;
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for (i = L0; i < CPUFREQ_LEVEL_END; i++) {
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exynos5250_clkdiv_table[i].index = i;
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tmp = __raw_readl(EXYNOS5_CLKDIV_CPU0);
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tmp &= ~((0x7 << 0) | (0x7 << 4) | (0x7 << 8) |
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(0x7 << 12) | (0x7 << 16) | (0x7 << 20) |
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(0x7 << 24) | (0x7 << 28));
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tmp |= ((clkdiv_cpu0_5250[i][0] << 0) |
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(clkdiv_cpu0_5250[i][1] << 4) |
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(clkdiv_cpu0_5250[i][2] << 8) |
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(clkdiv_cpu0_5250[i][3] << 12) |
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(clkdiv_cpu0_5250[i][4] << 16) |
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(clkdiv_cpu0_5250[i][5] << 20) |
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(clkdiv_cpu0_5250[i][6] << 24) |
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(clkdiv_cpu0_5250[i][7] << 28));
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exynos5250_clkdiv_table[i].clkdiv = tmp;
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tmp = __raw_readl(EXYNOS5_CLKDIV_CPU1);
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tmp &= ~((0x7 << 0) | (0x7 << 4));
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tmp |= ((clkdiv_cpu1_5250[i][0] << 0) |
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(clkdiv_cpu1_5250[i][1] << 4));
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exynos5250_clkdiv_table[i].clkdiv1 = tmp;
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}
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info->mpll_freq_khz = rate;
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/* 1000Mhz */
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info->pm_lock_idx = L7;
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/* 800Mhz */
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info->pll_safe_idx = L9;
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info->max_support_idx = max_support_idx;
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info->min_support_idx = min_support_idx;
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info->cpu_clk = cpu_clk;
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info->volt_table = exynos5250_volt_table;
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info->freq_table = exynos5250_freq_table;
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info->set_freq = exynos5250_set_frequency;
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info->need_apll_change = exynos5250_pms_change;
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return 0;
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err_mout_apll:
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clk_put(mout_mpll);
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err_mout_mpll:
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clk_put(moutcore);
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err_moutcore:
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clk_put(cpu_clk);
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pr_err("%s: failed initialization\n", __func__);
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return -EINVAL;
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}
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EXPORT_SYMBOL(exynos5250_cpufreq_init);
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