635 lines
17 KiB
C
635 lines
17 KiB
C
/*
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* Memory arbiter functions. Allocates bandwidth through the
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* arbiter and sets up arbiter breakpoints.
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*
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* The algorithm first assigns slots to the clients that has specified
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* bandwidth (e.g. ethernet) and then the remaining slots are divided
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* on all the active clients.
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*
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* Copyright (c) 2004-2007 Axis Communications AB.
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*
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* The artpec-3 has two arbiters. The memory hierarchy looks like this:
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*
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*
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* CPU DMAs
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* | |
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* | |
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* -------------- ------------------
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* | foo arbiter|----| Internal memory|
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* -------------- ------------------
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* |
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* --------------
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* | L2 cache |
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* --------------
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* |
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* h264 etc |
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* | |
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* | |
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* --------------
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* | bar arbiter|
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* --------------
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* |
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* ---------
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* | SDRAM |
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* ---------
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*
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*/
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#include <hwregs/reg_map.h>
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#include <hwregs/reg_rdwr.h>
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#include <hwregs/marb_foo_defs.h>
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#include <hwregs/marb_bar_defs.h>
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#include <arbiter.h>
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#include <hwregs/intr_vect.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/signal.h>
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#include <linux/errno.h>
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#include <linux/spinlock.h>
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#include <asm/io.h>
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#include <asm/irq_regs.h>
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#define D(x)
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struct crisv32_watch_entry {
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unsigned long instance;
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watch_callback *cb;
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unsigned long start;
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unsigned long end;
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int used;
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};
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#define NUMBER_OF_BP 4
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#define SDRAM_BANDWIDTH 400000000
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#define INTMEM_BANDWIDTH 400000000
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#define NBR_OF_SLOTS 64
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#define NBR_OF_REGIONS 2
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#define NBR_OF_CLIENTS 15
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#define ARBITERS 2
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#define UNASSIGNED 100
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struct arbiter {
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unsigned long instance;
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int nbr_regions;
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int nbr_clients;
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int requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS];
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int active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS];
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};
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static struct crisv32_watch_entry watches[ARBITERS][NUMBER_OF_BP] =
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{
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{
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{regi_marb_foo_bp0},
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{regi_marb_foo_bp1},
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{regi_marb_foo_bp2},
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{regi_marb_foo_bp3}
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},
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{
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{regi_marb_bar_bp0},
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{regi_marb_bar_bp1},
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{regi_marb_bar_bp2},
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{regi_marb_bar_bp3}
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}
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};
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struct arbiter arbiters[ARBITERS] =
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{
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{ /* L2 cache arbiter */
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.instance = regi_marb_foo,
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.nbr_regions = 2,
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.nbr_clients = 15
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},
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{ /* DDR2 arbiter */
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.instance = regi_marb_bar,
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.nbr_regions = 1,
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.nbr_clients = 9
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}
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};
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static int max_bandwidth[NBR_OF_REGIONS] = {SDRAM_BANDWIDTH, INTMEM_BANDWIDTH};
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DEFINE_SPINLOCK(arbiter_lock);
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static irqreturn_t
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crisv32_foo_arbiter_irq(int irq, void *dev_id);
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static irqreturn_t
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crisv32_bar_arbiter_irq(int irq, void *dev_id);
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/*
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* "I'm the arbiter, I know the score.
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* From square one I'll be watching all 64."
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* (memory arbiter slots, that is)
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*
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* Or in other words:
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* Program the memory arbiter slots for "region" according to what's
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* in requested_slots[] and active_clients[], while minimizing
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* latency. A caller may pass a non-zero positive amount for
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* "unused_slots", which must then be the unallocated, remaining
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* number of slots, free to hand out to any client.
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*/
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static void crisv32_arbiter_config(int arbiter, int region, int unused_slots)
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{
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int slot;
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int client;
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int interval = 0;
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/*
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* This vector corresponds to the hardware arbiter slots (see
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* the hardware documentation for semantics). We initialize
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* each slot with a suitable sentinel value outside the valid
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* range {0 .. NBR_OF_CLIENTS - 1} and replace them with
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* client indexes. Then it's fed to the hardware.
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*/
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s8 val[NBR_OF_SLOTS];
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for (slot = 0; slot < NBR_OF_SLOTS; slot++)
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val[slot] = -1;
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for (client = 0; client < arbiters[arbiter].nbr_clients; client++) {
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int pos;
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/* Allocate the requested non-zero number of slots, but
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* also give clients with zero-requests one slot each
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* while stocks last. We do the latter here, in client
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* order. This makes sure zero-request clients are the
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* first to get to any spare slots, else those slots
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* could, when bandwidth is allocated close to the limit,
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* all be allocated to low-index non-zero-request clients
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* in the default-fill loop below. Another positive but
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* secondary effect is a somewhat better spread of the
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* zero-bandwidth clients in the vector, avoiding some of
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* the latency that could otherwise be caused by the
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* partitioning of non-zero-bandwidth clients at low
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* indexes and zero-bandwidth clients at high
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* indexes. (Note that this spreading can only affect the
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* unallocated bandwidth.) All the above only matters for
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* memory-intensive situations, of course.
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*/
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if (!arbiters[arbiter].requested_slots[region][client]) {
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/*
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* Skip inactive clients. Also skip zero-slot
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* allocations in this pass when there are no known
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* free slots.
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*/
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if (!arbiters[arbiter].active_clients[region][client] ||
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unused_slots <= 0)
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continue;
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unused_slots--;
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/* Only allocate one slot for this client. */
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interval = NBR_OF_SLOTS;
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} else
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interval = NBR_OF_SLOTS /
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arbiters[arbiter].requested_slots[region][client];
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pos = 0;
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while (pos < NBR_OF_SLOTS) {
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if (val[pos] >= 0)
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pos++;
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else {
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val[pos] = client;
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pos += interval;
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}
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}
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}
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client = 0;
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for (slot = 0; slot < NBR_OF_SLOTS; slot++) {
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/*
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* Allocate remaining slots in round-robin
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* client-number order for active clients. For this
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* pass, we ignore requested bandwidth and previous
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* allocations.
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*/
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if (val[slot] < 0) {
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int first = client;
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while (!arbiters[arbiter].active_clients[region][client]) {
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client = (client + 1) %
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arbiters[arbiter].nbr_clients;
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if (client == first)
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break;
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}
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val[slot] = client;
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client = (client + 1) % arbiters[arbiter].nbr_clients;
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}
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if (arbiter == 0) {
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if (region == EXT_REGION)
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REG_WR_INT_VECT(marb_foo, regi_marb_foo,
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rw_l2_slots, slot, val[slot]);
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else if (region == INT_REGION)
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REG_WR_INT_VECT(marb_foo, regi_marb_foo,
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rw_intm_slots, slot, val[slot]);
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} else {
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REG_WR_INT_VECT(marb_bar, regi_marb_bar,
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rw_ddr2_slots, slot, val[slot]);
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}
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}
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}
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extern char _stext, _etext;
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static void crisv32_arbiter_init(void)
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{
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static int initialized;
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if (initialized)
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return;
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initialized = 1;
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/*
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* CPU caches are always set to active, but with zero
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* bandwidth allocated. It should be ok to allocate zero
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* bandwidth for the caches, because DMA for other channels
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* will supposedly finish, once their programmed amount is
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* done, and then the caches will get access according to the
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* "fixed scheme" for unclaimed slots. Though, if for some
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* use-case somewhere, there's a maximum CPU latency for
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* e.g. some interrupt, we have to start allocating specific
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* bandwidth for the CPU caches too.
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*/
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arbiters[0].active_clients[EXT_REGION][11] = 1;
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arbiters[0].active_clients[EXT_REGION][12] = 1;
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crisv32_arbiter_config(0, EXT_REGION, 0);
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crisv32_arbiter_config(0, INT_REGION, 0);
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crisv32_arbiter_config(1, EXT_REGION, 0);
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if (request_irq(MEMARB_FOO_INTR_VECT, crisv32_foo_arbiter_irq,
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0, "arbiter", NULL))
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printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
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if (request_irq(MEMARB_BAR_INTR_VECT, crisv32_bar_arbiter_irq,
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0, "arbiter", NULL))
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printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
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#ifndef CONFIG_ETRAX_KGDB
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/* Global watch for writes to kernel text segment. */
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crisv32_arbiter_watch(virt_to_phys(&_stext), &_etext - &_stext,
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MARB_CLIENTS(arbiter_all_clients, arbiter_bar_all_clients),
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arbiter_all_write, NULL);
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#endif
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/* Set up max burst sizes by default */
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REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_rd_burst, 3);
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REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_wr_burst, 3);
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REG_WR_INT(marb_bar, regi_marb_bar, rw_ccd_burst, 3);
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REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_wr_burst, 3);
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REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_rd_burst, 3);
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REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_rd_burst, 3);
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REG_WR_INT(marb_bar, regi_marb_bar, rw_vout_burst, 3);
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REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_fifo_burst, 3);
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REG_WR_INT(marb_bar, regi_marb_bar, rw_l2cache_burst, 3);
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}
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int crisv32_arbiter_allocate_bandwidth(int client, int region,
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unsigned long bandwidth)
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{
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int i;
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int total_assigned = 0;
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int total_clients = 0;
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int req;
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int arbiter = 0;
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crisv32_arbiter_init();
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if (client & 0xffff0000) {
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arbiter = 1;
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client >>= 16;
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}
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for (i = 0; i < arbiters[arbiter].nbr_clients; i++) {
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total_assigned += arbiters[arbiter].requested_slots[region][i];
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total_clients += arbiters[arbiter].active_clients[region][i];
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}
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/* Avoid division by 0 for 0-bandwidth requests. */
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req = bandwidth == 0
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? 0 : NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth);
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/*
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* We make sure that there are enough slots only for non-zero
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* requests. Requesting 0 bandwidth *may* allocate slots,
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* though if all bandwidth is allocated, such a client won't
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* get any and will have to rely on getting memory access
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* according to the fixed scheme that's the default when one
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* of the slot-allocated clients doesn't claim their slot.
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*/
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if (total_assigned + req > NBR_OF_SLOTS)
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return -ENOMEM;
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arbiters[arbiter].active_clients[region][client] = 1;
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arbiters[arbiter].requested_slots[region][client] = req;
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crisv32_arbiter_config(arbiter, region, NBR_OF_SLOTS - total_assigned);
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/* Propagate allocation from foo to bar */
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if (arbiter == 0)
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crisv32_arbiter_allocate_bandwidth(8 << 16,
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EXT_REGION, bandwidth);
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return 0;
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}
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/*
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* Main entry for bandwidth deallocation.
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*
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* Strictly speaking, for a somewhat constant set of clients where
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* each client gets a constant bandwidth and is just enabled or
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* disabled (somewhat dynamically), no action is necessary here to
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* avoid starvation for non-zero-allocation clients, as the allocated
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* slots will just be unused. However, handing out those unused slots
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* to active clients avoids needless latency if the "fixed scheme"
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* would give unclaimed slots to an eager low-index client.
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*/
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void crisv32_arbiter_deallocate_bandwidth(int client, int region)
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{
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int i;
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int total_assigned = 0;
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int arbiter = 0;
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if (client & 0xffff0000)
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arbiter = 1;
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arbiters[arbiter].requested_slots[region][client] = 0;
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arbiters[arbiter].active_clients[region][client] = 0;
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for (i = 0; i < arbiters[arbiter].nbr_clients; i++)
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total_assigned += arbiters[arbiter].requested_slots[region][i];
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crisv32_arbiter_config(arbiter, region, NBR_OF_SLOTS - total_assigned);
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}
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int crisv32_arbiter_watch(unsigned long start, unsigned long size,
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unsigned long clients, unsigned long accesses,
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watch_callback *cb)
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{
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int i;
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int arbiter;
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int used[2];
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int ret = 0;
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crisv32_arbiter_init();
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if (start > 0x80000000) {
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printk(KERN_ERR "Arbiter: %lX doesn't look like a "
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"physical address", start);
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return -EFAULT;
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}
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spin_lock(&arbiter_lock);
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if (clients & 0xffff)
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used[0] = 1;
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if (clients & 0xffff0000)
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used[1] = 1;
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for (arbiter = 0; arbiter < ARBITERS; arbiter++) {
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if (!used[arbiter])
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continue;
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for (i = 0; i < NUMBER_OF_BP; i++) {
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if (!watches[arbiter][i].used) {
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unsigned intr_mask;
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if (arbiter)
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intr_mask = REG_RD_INT(marb_bar,
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regi_marb_bar, rw_intr_mask);
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else
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intr_mask = REG_RD_INT(marb_foo,
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regi_marb_foo, rw_intr_mask);
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watches[arbiter][i].used = 1;
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watches[arbiter][i].start = start;
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watches[arbiter][i].end = start + size;
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watches[arbiter][i].cb = cb;
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ret |= (i + 1) << (arbiter + 8);
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if (arbiter) {
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REG_WR_INT(marb_bar_bp,
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watches[arbiter][i].instance,
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rw_first_addr,
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watches[arbiter][i].start);
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REG_WR_INT(marb_bar_bp,
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watches[arbiter][i].instance,
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rw_last_addr,
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watches[arbiter][i].end);
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REG_WR_INT(marb_bar_bp,
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watches[arbiter][i].instance,
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rw_op, accesses);
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REG_WR_INT(marb_bar_bp,
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watches[arbiter][i].instance,
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rw_clients,
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clients & 0xffff);
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} else {
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REG_WR_INT(marb_foo_bp,
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watches[arbiter][i].instance,
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rw_first_addr,
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watches[arbiter][i].start);
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REG_WR_INT(marb_foo_bp,
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watches[arbiter][i].instance,
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rw_last_addr,
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watches[arbiter][i].end);
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REG_WR_INT(marb_foo_bp,
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watches[arbiter][i].instance,
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rw_op, accesses);
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REG_WR_INT(marb_foo_bp,
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watches[arbiter][i].instance,
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rw_clients, clients >> 16);
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}
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if (i == 0)
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intr_mask |= 1;
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else if (i == 1)
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intr_mask |= 2;
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else if (i == 2)
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intr_mask |= 4;
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else if (i == 3)
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intr_mask |= 8;
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if (arbiter)
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REG_WR_INT(marb_bar, regi_marb_bar,
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rw_intr_mask, intr_mask);
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else
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REG_WR_INT(marb_foo, regi_marb_foo,
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rw_intr_mask, intr_mask);
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spin_unlock(&arbiter_lock);
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break;
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}
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}
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}
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spin_unlock(&arbiter_lock);
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if (ret)
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return ret;
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else
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return -ENOMEM;
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}
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int crisv32_arbiter_unwatch(int id)
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{
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int arbiter;
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int intr_mask;
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crisv32_arbiter_init();
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spin_lock(&arbiter_lock);
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for (arbiter = 0; arbiter < ARBITERS; arbiter++) {
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int id2;
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if (arbiter)
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intr_mask = REG_RD_INT(marb_bar, regi_marb_bar,
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rw_intr_mask);
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else
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intr_mask = REG_RD_INT(marb_foo, regi_marb_foo,
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rw_intr_mask);
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id2 = (id & (0xff << (arbiter + 8))) >> (arbiter + 8);
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if (id2 == 0)
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continue;
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id2--;
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if ((id2 >= NUMBER_OF_BP) || (!watches[arbiter][id2].used)) {
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spin_unlock(&arbiter_lock);
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return -EINVAL;
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}
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memset(&watches[arbiter][id2], 0,
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sizeof(struct crisv32_watch_entry));
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if (id2 == 0)
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intr_mask &= ~1;
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else if (id2 == 1)
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intr_mask &= ~2;
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else if (id2 == 2)
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intr_mask &= ~4;
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else if (id2 == 3)
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intr_mask &= ~8;
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if (arbiter)
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REG_WR_INT(marb_bar, regi_marb_bar, rw_intr_mask,
|
|
intr_mask);
|
|
else
|
|
REG_WR_INT(marb_foo, regi_marb_foo, rw_intr_mask,
|
|
intr_mask);
|
|
}
|
|
|
|
spin_unlock(&arbiter_lock);
|
|
return 0;
|
|
}
|
|
|
|
extern void show_registers(struct pt_regs *regs);
|
|
|
|
|
|
static irqreturn_t
|
|
crisv32_foo_arbiter_irq(int irq, void *dev_id)
|
|
{
|
|
reg_marb_foo_r_masked_intr masked_intr =
|
|
REG_RD(marb_foo, regi_marb_foo, r_masked_intr);
|
|
reg_marb_foo_bp_r_brk_clients r_clients;
|
|
reg_marb_foo_bp_r_brk_addr r_addr;
|
|
reg_marb_foo_bp_r_brk_op r_op;
|
|
reg_marb_foo_bp_r_brk_first_client r_first;
|
|
reg_marb_foo_bp_r_brk_size r_size;
|
|
reg_marb_foo_bp_rw_ack ack = {0};
|
|
reg_marb_foo_rw_ack_intr ack_intr = {
|
|
.bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1
|
|
};
|
|
struct crisv32_watch_entry *watch;
|
|
unsigned arbiter = (unsigned)dev_id;
|
|
|
|
masked_intr = REG_RD(marb_foo, regi_marb_foo, r_masked_intr);
|
|
|
|
if (masked_intr.bp0)
|
|
watch = &watches[arbiter][0];
|
|
else if (masked_intr.bp1)
|
|
watch = &watches[arbiter][1];
|
|
else if (masked_intr.bp2)
|
|
watch = &watches[arbiter][2];
|
|
else if (masked_intr.bp3)
|
|
watch = &watches[arbiter][3];
|
|
else
|
|
return IRQ_NONE;
|
|
|
|
/* Retrieve all useful information and print it. */
|
|
r_clients = REG_RD(marb_foo_bp, watch->instance, r_brk_clients);
|
|
r_addr = REG_RD(marb_foo_bp, watch->instance, r_brk_addr);
|
|
r_op = REG_RD(marb_foo_bp, watch->instance, r_brk_op);
|
|
r_first = REG_RD(marb_foo_bp, watch->instance, r_brk_first_client);
|
|
r_size = REG_RD(marb_foo_bp, watch->instance, r_brk_size);
|
|
|
|
printk(KERN_DEBUG "Arbiter IRQ\n");
|
|
printk(KERN_DEBUG "Clients %X addr %X op %X first %X size %X\n",
|
|
REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_clients, r_clients),
|
|
REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_addr, r_addr),
|
|
REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_op, r_op),
|
|
REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_first_client, r_first),
|
|
REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_size, r_size));
|
|
|
|
REG_WR(marb_foo_bp, watch->instance, rw_ack, ack);
|
|
REG_WR(marb_foo, regi_marb_foo, rw_ack_intr, ack_intr);
|
|
|
|
printk(KERN_DEBUG "IRQ occurred at %X\n", (unsigned)get_irq_regs());
|
|
|
|
if (watch->cb)
|
|
watch->cb();
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t
|
|
crisv32_bar_arbiter_irq(int irq, void *dev_id)
|
|
{
|
|
reg_marb_bar_r_masked_intr masked_intr =
|
|
REG_RD(marb_bar, regi_marb_bar, r_masked_intr);
|
|
reg_marb_bar_bp_r_brk_clients r_clients;
|
|
reg_marb_bar_bp_r_brk_addr r_addr;
|
|
reg_marb_bar_bp_r_brk_op r_op;
|
|
reg_marb_bar_bp_r_brk_first_client r_first;
|
|
reg_marb_bar_bp_r_brk_size r_size;
|
|
reg_marb_bar_bp_rw_ack ack = {0};
|
|
reg_marb_bar_rw_ack_intr ack_intr = {
|
|
.bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1
|
|
};
|
|
struct crisv32_watch_entry *watch;
|
|
unsigned arbiter = (unsigned)dev_id;
|
|
|
|
masked_intr = REG_RD(marb_bar, regi_marb_bar, r_masked_intr);
|
|
|
|
if (masked_intr.bp0)
|
|
watch = &watches[arbiter][0];
|
|
else if (masked_intr.bp1)
|
|
watch = &watches[arbiter][1];
|
|
else if (masked_intr.bp2)
|
|
watch = &watches[arbiter][2];
|
|
else if (masked_intr.bp3)
|
|
watch = &watches[arbiter][3];
|
|
else
|
|
return IRQ_NONE;
|
|
|
|
/* Retrieve all useful information and print it. */
|
|
r_clients = REG_RD(marb_bar_bp, watch->instance, r_brk_clients);
|
|
r_addr = REG_RD(marb_bar_bp, watch->instance, r_brk_addr);
|
|
r_op = REG_RD(marb_bar_bp, watch->instance, r_brk_op);
|
|
r_first = REG_RD(marb_bar_bp, watch->instance, r_brk_first_client);
|
|
r_size = REG_RD(marb_bar_bp, watch->instance, r_brk_size);
|
|
|
|
printk(KERN_DEBUG "Arbiter IRQ\n");
|
|
printk(KERN_DEBUG "Clients %X addr %X op %X first %X size %X\n",
|
|
REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_clients, r_clients),
|
|
REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_addr, r_addr),
|
|
REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_op, r_op),
|
|
REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_first_client, r_first),
|
|
REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_size, r_size));
|
|
|
|
REG_WR(marb_bar_bp, watch->instance, rw_ack, ack);
|
|
REG_WR(marb_bar, regi_marb_bar, rw_ack_intr, ack_intr);
|
|
|
|
printk(KERN_DEBUG "IRQ occurred at %X\n", (unsigned)get_irq_regs()->erp);
|
|
|
|
if (watch->cb)
|
|
watch->cb();
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|