253 lines
7.2 KiB
C
253 lines
7.2 KiB
C
#ifndef _ASM_POWERPC_NOHASH_PGTABLE_H
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#define _ASM_POWERPC_NOHASH_PGTABLE_H
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#if defined(CONFIG_PPC64)
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#include <asm/nohash/64/pgtable.h>
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#else
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#include <asm/nohash/32/pgtable.h>
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#endif
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#ifndef __ASSEMBLY__
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/* Generic accessors to PTE bits */
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static inline int pte_write(pte_t pte)
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{
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return (pte_val(pte) & (_PAGE_RW | _PAGE_RO)) != _PAGE_RO;
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}
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static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
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static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
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static inline int pte_special(pte_t pte) { return pte_val(pte) & _PAGE_SPECIAL; }
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static inline int pte_none(pte_t pte) { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
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static inline pgprot_t pte_pgprot(pte_t pte) { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
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#ifdef CONFIG_NUMA_BALANCING
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/*
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* These work without NUMA balancing but the kernel does not care. See the
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* comment in include/asm-generic/pgtable.h . On powerpc, this will only
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* work for user pages and always return true for kernel pages.
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*/
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static inline int pte_protnone(pte_t pte)
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{
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return (pte_val(pte) &
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(_PAGE_PRESENT | _PAGE_USER)) == _PAGE_PRESENT;
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}
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static inline int pmd_protnone(pmd_t pmd)
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{
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return pte_protnone(pmd_pte(pmd));
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}
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#endif /* CONFIG_NUMA_BALANCING */
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static inline int pte_present(pte_t pte)
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{
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return pte_val(pte) & _PAGE_PRESENT;
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}
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/* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*
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* Even if PTEs can be unsigned long long, a PFN is always an unsigned
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* long for now.
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*/
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static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot) {
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return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
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pgprot_val(pgprot)); }
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static inline unsigned long pte_pfn(pte_t pte) {
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return pte_val(pte) >> PTE_RPN_SHIFT; }
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/* Generic modifiers for PTE bits */
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static inline pte_t pte_wrprotect(pte_t pte)
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{
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pte_basic_t ptev;
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ptev = pte_val(pte) & ~(_PAGE_RW | _PAGE_HWWRITE);
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ptev |= _PAGE_RO;
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return __pte(ptev);
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}
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static inline pte_t pte_mkclean(pte_t pte)
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{
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return __pte(pte_val(pte) & ~(_PAGE_DIRTY | _PAGE_HWWRITE));
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}
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static inline pte_t pte_mkold(pte_t pte)
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{
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return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
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}
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static inline pte_t pte_mkwrite(pte_t pte)
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{
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pte_basic_t ptev;
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ptev = pte_val(pte) & ~_PAGE_RO;
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ptev |= _PAGE_RW;
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return __pte(ptev);
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}
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static inline pte_t pte_mkdirty(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_DIRTY);
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}
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static inline pte_t pte_mkyoung(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_ACCESSED);
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}
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static inline pte_t pte_mkspecial(pte_t pte)
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{
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return __pte(pte_val(pte) | _PAGE_SPECIAL);
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}
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static inline pte_t pte_mkhuge(pte_t pte)
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{
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return pte;
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}
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
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}
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/* Insert a PTE, top-level function is out of line. It uses an inline
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* low level function in the respective pgtable-* files
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*/
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extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
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pte_t pte);
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/* This low level function performs the actual PTE insertion
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* Setting the PTE depends on the MMU type and other factors. It's
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* an horrible mess that I'm not going to try to clean up now but
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* I'm keeping it in one place rather than spread around
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*/
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static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte, int percpu)
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{
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#if defined(CONFIG_PPC_STD_MMU_32) && defined(CONFIG_SMP) && !defined(CONFIG_PTE_64BIT)
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/* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the
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* helper pte_update() which does an atomic update. We need to do that
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* because a concurrent invalidation can clear _PAGE_HASHPTE. If it's a
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* per-CPU PTE such as a kmap_atomic, we do a simple update preserving
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* the hash bits instead (ie, same as the non-SMP case)
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*/
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if (percpu)
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*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
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| (pte_val(pte) & ~_PAGE_HASHPTE));
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else
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pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
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#elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
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/* Second case is 32-bit with 64-bit PTE. In this case, we
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* can just store as long as we do the two halves in the right order
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* with a barrier in between. This is possible because we take care,
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* in the hash code, to pre-invalidate if the PTE was already hashed,
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* which synchronizes us with any concurrent invalidation.
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* In the percpu case, we also fallback to the simple update preserving
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* the hash bits
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*/
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if (percpu) {
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*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
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| (pte_val(pte) & ~_PAGE_HASHPTE));
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return;
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}
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#if _PAGE_HASHPTE != 0
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if (pte_val(*ptep) & _PAGE_HASHPTE)
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flush_hash_entry(mm, ptep, addr);
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#endif
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__asm__ __volatile__("\
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stw%U0%X0 %2,%0\n\
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eieio\n\
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stw%U0%X0 %L2,%1"
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: "=m" (*ptep), "=m" (*((unsigned char *)ptep+4))
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: "r" (pte) : "memory");
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#elif defined(CONFIG_PPC_STD_MMU_32)
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/* Third case is 32-bit hash table in UP mode, we need to preserve
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* the _PAGE_HASHPTE bit since we may not have invalidated the previous
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* translation in the hash yet (done in a subsequent flush_tlb_xxx())
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* and see we need to keep track that this PTE needs invalidating
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*/
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*ptep = __pte((pte_val(*ptep) & _PAGE_HASHPTE)
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| (pte_val(pte) & ~_PAGE_HASHPTE));
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#else
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/* Anything else just stores the PTE normally. That covers all 64-bit
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* cases, and 32-bit non-hash with 32-bit PTEs.
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*/
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*ptep = pte;
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#ifdef CONFIG_PPC_BOOK3E_64
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/*
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* With hardware tablewalk, a sync is needed to ensure that
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* subsequent accesses see the PTE we just wrote. Unlike userspace
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* mappings, we can't tolerate spurious faults, so make sure
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* the new PTE will be seen the first time.
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*/
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if (is_kernel_addr(addr))
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mb();
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#endif
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#endif
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}
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#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
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extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
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pte_t *ptep, pte_t entry, int dirty);
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/*
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* Macro to mark a page protection value as "uncacheable".
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*/
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#define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
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_PAGE_WRITETHRU)
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#define pgprot_noncached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_NO_CACHE | _PAGE_GUARDED))
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#define pgprot_noncached_wc(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_NO_CACHE))
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#define pgprot_cached(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_COHERENT))
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#define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
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_PAGE_COHERENT | _PAGE_WRITETHRU))
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#define pgprot_cached_noncoherent(prot) \
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(__pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL))
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#define pgprot_writecombine pgprot_noncached_wc
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struct file;
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extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
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unsigned long size, pgprot_t vma_prot);
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#define __HAVE_PHYS_MEM_ACCESS_PROT
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#ifdef CONFIG_HUGETLB_PAGE
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static inline int hugepd_ok(hugepd_t hpd)
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{
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return (hpd.pd > 0);
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}
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static inline int pmd_huge(pmd_t pmd)
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{
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return 0;
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}
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static inline int pud_huge(pud_t pud)
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{
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return 0;
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}
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static inline int pgd_huge(pgd_t pgd)
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{
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return 0;
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}
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#define pgd_huge pgd_huge
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#define is_hugepd(hpd) (hugepd_ok(hpd))
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#endif
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#endif /* __ASSEMBLY__ */
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#endif
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