164 lines
3.6 KiB
C
164 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2015 Chen-Yu Tsai
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*
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* Chen-Yu Tsai <wens@csie.org>
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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static DEFINE_SPINLOCK(ve_lock);
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#define SUN4I_VE_ENABLE 31
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#define SUN4I_VE_DIVIDER_SHIFT 16
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#define SUN4I_VE_DIVIDER_WIDTH 3
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#define SUN4I_VE_RESET 0
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/*
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* sunxi_ve_reset... - reset bit in ve clk registers handling
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*/
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struct ve_reset_data {
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void __iomem *reg;
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spinlock_t *lock;
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struct reset_controller_dev rcdev;
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};
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static int sunxi_ve_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct ve_reset_data *data = container_of(rcdev,
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struct ve_reset_data,
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rcdev);
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(data->lock, flags);
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reg = readl(data->reg);
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writel(reg & ~BIT(SUN4I_VE_RESET), data->reg);
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spin_unlock_irqrestore(data->lock, flags);
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return 0;
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}
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static int sunxi_ve_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct ve_reset_data *data = container_of(rcdev,
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struct ve_reset_data,
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rcdev);
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(data->lock, flags);
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reg = readl(data->reg);
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writel(reg | BIT(SUN4I_VE_RESET), data->reg);
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spin_unlock_irqrestore(data->lock, flags);
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return 0;
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}
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static int sunxi_ve_of_xlate(struct reset_controller_dev *rcdev,
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const struct of_phandle_args *reset_spec)
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{
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if (WARN_ON(reset_spec->args_count != 0))
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return -EINVAL;
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return 0;
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}
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static const struct reset_control_ops sunxi_ve_reset_ops = {
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.assert = sunxi_ve_reset_assert,
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.deassert = sunxi_ve_reset_deassert,
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};
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static void __init sun4i_ve_clk_setup(struct device_node *node)
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{
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struct clk *clk;
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struct clk_divider *div;
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struct clk_gate *gate;
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struct ve_reset_data *reset_data;
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const char *parent;
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const char *clk_name = node->name;
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void __iomem *reg;
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int err;
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reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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if (IS_ERR(reg))
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return;
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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goto err_unmap;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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goto err_free_div;
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of_property_read_string(node, "clock-output-names", &clk_name);
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parent = of_clk_get_parent_name(node, 0);
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gate->reg = reg;
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gate->bit_idx = SUN4I_VE_ENABLE;
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gate->lock = &ve_lock;
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div->reg = reg;
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div->shift = SUN4I_VE_DIVIDER_SHIFT;
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div->width = SUN4I_VE_DIVIDER_WIDTH;
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div->lock = &ve_lock;
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clk = clk_register_composite(NULL, clk_name, &parent, 1,
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NULL, NULL,
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&div->hw, &clk_divider_ops,
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&gate->hw, &clk_gate_ops,
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CLK_SET_RATE_PARENT);
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if (IS_ERR(clk))
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goto err_free_gate;
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err = of_clk_add_provider(node, of_clk_src_simple_get, clk);
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if (err)
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goto err_unregister_clk;
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reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
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if (!reset_data)
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goto err_del_provider;
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reset_data->reg = reg;
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reset_data->lock = &ve_lock;
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reset_data->rcdev.nr_resets = 1;
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reset_data->rcdev.ops = &sunxi_ve_reset_ops;
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reset_data->rcdev.of_node = node;
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reset_data->rcdev.of_xlate = sunxi_ve_of_xlate;
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reset_data->rcdev.of_reset_n_cells = 0;
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err = reset_controller_register(&reset_data->rcdev);
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if (err)
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goto err_free_reset;
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return;
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err_free_reset:
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kfree(reset_data);
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err_del_provider:
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of_clk_del_provider(node);
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err_unregister_clk:
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clk_unregister(clk);
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err_free_gate:
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kfree(gate);
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err_free_div:
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kfree(div);
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err_unmap:
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iounmap(reg);
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}
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CLK_OF_DECLARE(sun4i_ve, "allwinner,sun4i-a10-ve-clk",
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sun4i_ve_clk_setup);
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