261 lines
6.6 KiB
Plaintext
261 lines
6.6 KiB
Plaintext
/*
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* Device Tree Source for UniPhier PH1-sLD3 SoC
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*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "socionext,ph1-sld3";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "socionext,uniphier-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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next-level-cache = <&l2>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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next-level-cache = <&l2>;
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};
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};
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clocks {
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refclk: ref {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24576000>;
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};
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arm_timer_clk: arm_timer_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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uart_clk: uart_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <36864000>;
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};
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iobus_clk: iobus_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <100000000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-parent = <&intc>;
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timer@20000200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x20000200 0x20>;
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interrupts = <1 11 0x304>;
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clocks = <&arm_timer_clk>;
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};
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timer@20000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x20000600 0x20>;
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interrupts = <1 13 0x304>;
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clocks = <&arm_timer_clk>;
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};
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intc: interrupt-controller@20001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x20001000 0x1000>,
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<0x20000100 0x100>;
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};
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l2: l2-cache@500c0000 {
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compatible = "socionext,uniphier-system-cache";
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reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
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<0x506c0000 0x400>;
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interrupts = <0 174 4>, <0 175 4>;
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cache-unified;
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cache-size = <(512 * 1024)>;
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cache-sets = <256>;
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cache-line-size = <128>;
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cache-level = <2>;
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};
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serial0: serial@54006800 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006800 0x40>;
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interrupts = <0 33 4>;
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clocks = <&uart_clk>;
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fifo-size = <64>;
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};
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serial1: serial@54006900 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006900 0x40>;
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interrupts = <0 35 4>;
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clocks = <&uart_clk>;
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fifo-size = <64>;
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};
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serial2: serial@54006a00 {
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compatible = "socionext,uniphier-uart";
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status = "disabled";
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reg = <0x54006a00 0x40>;
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interrupts = <0 37 4>;
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clocks = <&uart_clk>;
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fifo-size = <64>;
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};
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i2c0: i2c@58400000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58400000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 41 1>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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i2c1: i2c@58480000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58480000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 42 1>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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i2c2: i2c@58500000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58500000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 43 1>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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i2c3: i2c@58580000 {
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compatible = "socionext,uniphier-i2c";
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status = "disabled";
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reg = <0x58580000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 44 1>;
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clocks = <&iobus_clk>;
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clock-frequency = <100000>;
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};
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/* chip-internal connection for DMD */
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i2c4: i2c@58600000 {
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compatible = "socionext,uniphier-i2c";
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reg = <0x58600000 0x40>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 45 1>;
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clocks = <&iobus_clk>;
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clock-frequency = <400000>;
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};
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system_bus: system-bus@58c00000 {
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compatible = "socionext,uniphier-system-bus";
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status = "disabled";
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reg = <0x58c00000 0x400>;
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#address-cells = <2>;
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#size-cells = <1>;
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};
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smpctrl@59800000 {
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compatible = "socionext,uniphier-smpctrl";
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reg = <0x59801000 0x400>;
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};
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usb0: usb@5a800100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a800100 0x100>;
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interrupts = <0 80 4>;
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};
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usb1: usb@5a810100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a810100 0x100>;
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interrupts = <0 81 4>;
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};
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usb2: usb@5a820100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a820100 0x100>;
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interrupts = <0 82 4>;
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};
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usb3: usb@5a830100 {
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compatible = "socionext,uniphier-ehci", "generic-ehci";
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status = "disabled";
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reg = <0x5a830100 0x100>;
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interrupts = <0 83 4>;
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};
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};
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};
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