182 lines
4.1 KiB
C
182 lines
4.1 KiB
C
/*
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* linux/arch/arm/mach-tegra/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* Copyright (C) 2009 Palm
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <asm/cacheflush.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach-types.h>
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#include <asm/smp_scu.h>
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#include <mach/powergate.h>
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#include "fuse.h"
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#include "flowctrl.h"
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#include "reset.h"
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#include "tegra_cpu_car.h"
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#include "common.h"
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#include "iomap.h"
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extern void tegra_secondary_startup(void);
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static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
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#define EVP_CPU_RESET_VECTOR \
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(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
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static void __cpuinit tegra_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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}
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static int tegra20_power_up_cpu(unsigned int cpu)
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{
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/* Enable the CPU clock. */
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tegra_enable_cpu_clock(cpu);
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/* Clear flow controller CSR. */
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flowctrl_write_cpu_csr(cpu, 0);
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return 0;
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}
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static int tegra30_power_up_cpu(unsigned int cpu)
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{
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int ret, pwrgateid;
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unsigned long timeout;
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pwrgateid = tegra_cpu_powergate_id(cpu);
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if (pwrgateid < 0)
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return pwrgateid;
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/* If this is the first boot, toggle powergates directly. */
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if (!tegra_powergate_is_powered(pwrgateid)) {
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ret = tegra_powergate_power_on(pwrgateid);
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if (ret)
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return ret;
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/* Wait for the power to come up. */
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timeout = jiffies + 10*HZ;
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while (tegra_powergate_is_powered(pwrgateid)) {
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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udelay(10);
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}
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}
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/* CPU partition is powered. Enable the CPU clock. */
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tegra_enable_cpu_clock(cpu);
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udelay(10);
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/* Remove I/O clamps. */
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ret = tegra_powergate_remove_clamping(pwrgateid);
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udelay(10);
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/* Clear flow controller CSR. */
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flowctrl_write_cpu_csr(cpu, 0);
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return 0;
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}
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static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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int status;
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/*
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* Force the CPU into reset. The CPU must remain in reset when the
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* flow controller state is cleared (which will cause the flow
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* controller to stop driving reset if the CPU has been power-gated
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* via the flow controller). This will have no effect on first boot
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* of the CPU since it should already be in reset.
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*/
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tegra_put_cpu_in_reset(cpu);
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/*
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* Unhalt the CPU. If the flow controller was used to power-gate the
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* CPU this will cause the flow controller to stop driving reset.
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* The CPU will remain in reset because the clock and reset block
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* is now driving reset.
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*/
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flowctrl_write_cpu_halt(cpu, 0);
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switch (tegra_chip_id) {
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case TEGRA20:
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status = tegra20_power_up_cpu(cpu);
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break;
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case TEGRA30:
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status = tegra30_power_up_cpu(cpu);
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break;
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default:
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status = -EINVAL;
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break;
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}
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if (status)
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goto done;
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/* Take the CPU out of reset. */
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tegra_cpu_out_of_reset(cpu);
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done:
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return status;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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static void __init tegra_smp_init_cpus(void)
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{
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unsigned int i, ncores = scu_get_core_count(scu_base);
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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set_smp_cross_call(gic_raise_softirq);
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}
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static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
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{
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tegra_cpu_reset_handler_init();
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scu_enable(scu_base);
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}
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struct smp_operations tegra_smp_ops __initdata = {
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.smp_init_cpus = tegra_smp_init_cpus,
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.smp_prepare_cpus = tegra_smp_prepare_cpus,
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.smp_secondary_init = tegra_secondary_init,
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.smp_boot_secondary = tegra_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = tegra_cpu_die,
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.cpu_disable = tegra_cpu_disable,
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#endif
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};
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