228 lines
6.0 KiB
C
228 lines
6.0 KiB
C
/*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#define gk20a_pmu(p) container_of((p), struct gk20a_pmu, base.subdev)
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#include "priv.h"
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#include <subdev/clk.h>
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#include <subdev/timer.h>
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#include <subdev/volt.h>
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#define BUSY_SLOT 0
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#define CLK_SLOT 7
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struct gk20a_pmu_dvfs_data {
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int p_load_target;
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int p_load_max;
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int p_smooth;
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unsigned int avg_load;
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};
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struct gk20a_pmu {
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struct nvkm_pmu base;
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struct nvkm_alarm alarm;
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struct gk20a_pmu_dvfs_data *data;
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};
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struct gk20a_pmu_dvfs_dev_status {
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unsigned long total;
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unsigned long busy;
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int cur_state;
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};
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static int
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gk20a_pmu_dvfs_target(struct gk20a_pmu *pmu, int *state)
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{
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struct nvkm_clk *clk = pmu->base.subdev.device->clk;
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return nvkm_clk_astate(clk, *state, 0, false);
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}
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static int
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gk20a_pmu_dvfs_get_cur_state(struct gk20a_pmu *pmu, int *state)
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{
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struct nvkm_clk *clk = pmu->base.subdev.device->clk;
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*state = clk->pstate;
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return 0;
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}
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static int
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gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu,
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int *state, int load)
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{
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struct gk20a_pmu_dvfs_data *data = pmu->data;
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struct nvkm_clk *clk = pmu->base.subdev.device->clk;
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int cur_level, level;
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/* For GK20A, the performance level is directly mapped to pstate */
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level = cur_level = clk->pstate;
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if (load > data->p_load_max) {
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level = min(clk->state_nr - 1, level + (clk->state_nr / 3));
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} else {
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level += ((load - data->p_load_target) * 10 /
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data->p_load_target) / 2;
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level = max(0, level);
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level = min(clk->state_nr - 1, level);
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}
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nvkm_trace(&pmu->base.subdev, "cur level = %d, new level = %d\n",
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cur_level, level);
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*state = level;
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if (level == cur_level)
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return 0;
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else
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return 1;
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}
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static int
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gk20a_pmu_dvfs_get_dev_status(struct gk20a_pmu *pmu,
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struct gk20a_pmu_dvfs_dev_status *status)
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{
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struct nvkm_device *device = pmu->base.subdev.device;
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status->busy = nvkm_rd32(device, 0x10a508 + (BUSY_SLOT * 0x10));
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status->total= nvkm_rd32(device, 0x10a508 + (CLK_SLOT * 0x10));
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return 0;
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}
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static void
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gk20a_pmu_dvfs_reset_dev_status(struct gk20a_pmu *pmu)
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{
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struct nvkm_device *device = pmu->base.subdev.device;
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nvkm_wr32(device, 0x10a508 + (BUSY_SLOT * 0x10), 0x80000000);
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nvkm_wr32(device, 0x10a508 + (CLK_SLOT * 0x10), 0x80000000);
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}
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static void
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gk20a_pmu_dvfs_work(struct nvkm_alarm *alarm)
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{
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struct gk20a_pmu *pmu =
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container_of(alarm, struct gk20a_pmu, alarm);
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struct gk20a_pmu_dvfs_data *data = pmu->data;
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struct gk20a_pmu_dvfs_dev_status status;
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struct nvkm_subdev *subdev = &pmu->base.subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_clk *clk = device->clk;
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struct nvkm_timer *tmr = device->timer;
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struct nvkm_volt *volt = device->volt;
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u32 utilization = 0;
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int state, ret;
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/*
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* The PMU is initialized before CLK and VOLT, so we have to make sure the
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* CLK and VOLT are ready here.
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*/
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if (!clk || !volt)
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goto resched;
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ret = gk20a_pmu_dvfs_get_dev_status(pmu, &status);
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if (ret) {
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nvkm_warn(subdev, "failed to get device status\n");
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goto resched;
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}
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if (status.total)
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utilization = div_u64((u64)status.busy * 100, status.total);
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data->avg_load = (data->p_smooth * data->avg_load) + utilization;
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data->avg_load /= data->p_smooth + 1;
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nvkm_trace(subdev, "utilization = %d %%, avg_load = %d %%\n",
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utilization, data->avg_load);
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ret = gk20a_pmu_dvfs_get_cur_state(pmu, &state);
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if (ret) {
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nvkm_warn(subdev, "failed to get current state\n");
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goto resched;
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}
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if (gk20a_pmu_dvfs_get_target_state(pmu, &state, data->avg_load)) {
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nvkm_trace(subdev, "set new state to %d\n", state);
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gk20a_pmu_dvfs_target(pmu, &state);
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}
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resched:
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gk20a_pmu_dvfs_reset_dev_status(pmu);
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nvkm_timer_alarm(tmr, 100000000, alarm);
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}
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static int
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gk20a_pmu_fini(struct nvkm_subdev *subdev, bool suspend)
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{
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struct gk20a_pmu *pmu = gk20a_pmu(subdev);
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nvkm_timer_alarm_cancel(subdev->device->timer, &pmu->alarm);
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return 0;
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}
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static void *
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gk20a_pmu_dtor(struct nvkm_subdev *subdev)
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{
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return gk20a_pmu(subdev);
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}
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static int
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gk20a_pmu_init(struct nvkm_subdev *subdev)
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{
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struct gk20a_pmu *pmu = gk20a_pmu(subdev);
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struct nvkm_device *device = pmu->base.subdev.device;
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/* init pwr perf counter */
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nvkm_wr32(device, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001);
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nvkm_wr32(device, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002);
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nvkm_wr32(device, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003);
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nvkm_timer_alarm(device->timer, 2000000000, &pmu->alarm);
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return 0;
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}
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static struct gk20a_pmu_dvfs_data
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gk20a_dvfs_data= {
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.p_load_target = 70,
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.p_load_max = 90,
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.p_smooth = 1,
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};
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static const struct nvkm_subdev_func
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gk20a_pmu = {
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.init = gk20a_pmu_init,
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.fini = gk20a_pmu_fini,
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.dtor = gk20a_pmu_dtor,
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};
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int
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gk20a_pmu_new(struct nvkm_device *device, int index, struct nvkm_pmu **ppmu)
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{
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static const struct nvkm_pmu_func func = {};
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struct gk20a_pmu *pmu;
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if (!(pmu = kzalloc(sizeof(*pmu), GFP_KERNEL)))
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return -ENOMEM;
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pmu->base.func = &func;
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*ppmu = &pmu->base;
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nvkm_subdev_ctor(&gk20a_pmu, device, index, &pmu->base.subdev);
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pmu->data = &gk20a_dvfs_data;
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nvkm_alarm_init(&pmu->alarm, gk20a_pmu_dvfs_work);
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return 0;
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}
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