699 lines
21 KiB
C
699 lines
21 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_PGTABLE_H
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#define __ASM_PGTABLE_H
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#include <asm/bug.h>
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#include <asm/proc-fns.h>
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#include <asm/memory.h>
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#include <asm/pgtable-hwdef.h>
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/*
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* Software defined PTE bits definition.
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*/
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#define PTE_VALID (_AT(pteval_t, 1) << 0)
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#define PTE_WRITE (PTE_DBM) /* same as DBM (51) */
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#define PTE_DIRTY (_AT(pteval_t, 1) << 55)
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#define PTE_SPECIAL (_AT(pteval_t, 1) << 56)
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#define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */
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/*
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* VMALLOC and SPARSEMEM_VMEMMAP ranges.
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*
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* VMEMAP_SIZE: allows the whole VA space to be covered by a struct page array
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* (rounded up to PUD_SIZE).
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* VMALLOC_START: beginning of the kernel VA space
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* VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space,
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* fixed mappings and modules
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*/
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#define VMEMMAP_SIZE ALIGN((1UL << (VA_BITS - PAGE_SHIFT)) * sizeof(struct page), PUD_SIZE)
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#ifndef CONFIG_KASAN
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#define VMALLOC_START (VA_START)
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#else
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#include <asm/kasan.h>
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#define VMALLOC_START (KASAN_SHADOW_END + SZ_64K)
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#endif
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#define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K)
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#define vmemmap ((struct page *)(VMALLOC_END + SZ_64K))
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#define FIRST_USER_ADDRESS 0UL
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#ifndef __ASSEMBLY__
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#include <linux/mmdebug.h>
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extern void __pte_error(const char *file, int line, unsigned long val);
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extern void __pmd_error(const char *file, int line, unsigned long val);
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extern void __pud_error(const char *file, int line, unsigned long val);
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extern void __pgd_error(const char *file, int line, unsigned long val);
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#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
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#define PROT_SECT_DEFAULT (PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
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#define PROT_DEVICE_nGnRnE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
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#define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_DEVICE_nGnRE))
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#define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
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#define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
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#define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
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#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
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#define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
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#define PROT_SECT_NORMAL_EXEC (PROT_SECT_DEFAULT | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
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#define _PAGE_DEFAULT (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL))
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#define PAGE_KERNEL __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE)
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#define PAGE_KERNEL_RO __pgprot(_PAGE_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_RDONLY)
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#define PAGE_KERNEL_ROX __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_RDONLY)
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#define PAGE_KERNEL_EXEC __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE)
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#define PAGE_KERNEL_EXEC_CONT __pgprot(_PAGE_DEFAULT | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_CONT)
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#define PAGE_HYP __pgprot(_PAGE_DEFAULT | PTE_HYP)
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#define PAGE_HYP_DEVICE __pgprot(PROT_DEVICE_nGnRE | PTE_HYP)
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#define PAGE_S2 __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_NORMAL) | PTE_S2_RDONLY)
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#define PAGE_S2_DEVICE __pgprot(PROT_DEFAULT | PTE_S2_MEMATTR(MT_S2_DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_UXN)
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#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_PXN | PTE_UXN)
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#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
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#define PAGE_SHARED_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_WRITE)
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#define PAGE_COPY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
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#define PAGE_COPY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
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#define PAGE_READONLY __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN)
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#define PAGE_READONLY_EXEC __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN)
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#define __P000 PAGE_NONE
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#define __P001 PAGE_READONLY
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#define __P010 PAGE_COPY
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#define __P011 PAGE_COPY
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#define __P100 PAGE_READONLY_EXEC
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#define __P101 PAGE_READONLY_EXEC
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#define __P110 PAGE_COPY_EXEC
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#define __P111 PAGE_COPY_EXEC
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#define __S000 PAGE_NONE
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#define __S001 PAGE_READONLY
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#define __S010 PAGE_SHARED
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#define __S011 PAGE_SHARED
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#define __S100 PAGE_READONLY_EXEC
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#define __S101 PAGE_READONLY_EXEC
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#define __S110 PAGE_SHARED_EXEC
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#define __S111 PAGE_SHARED_EXEC
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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extern struct page *empty_zero_page;
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#define ZERO_PAGE(vaddr) (empty_zero_page)
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#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
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#define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT)
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#define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
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#define pte_none(pte) (!pte_val(pte))
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#define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0))
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#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
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/* Find an entry in the third-level page table. */
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#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + pte_index(addr))
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#define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr))
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#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
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#define pte_unmap(pte) do { } while (0)
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#define pte_unmap_nested(pte) do { } while (0)
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/*
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* The following only work if pte_present(). Undefined behaviour otherwise.
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*/
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#define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)))
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#define pte_young(pte) (!!(pte_val(pte) & PTE_AF))
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#define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL))
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#define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE))
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#define pte_exec(pte) (!(pte_val(pte) & PTE_UXN))
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#define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT))
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#define pte_user(pte) (!!(pte_val(pte) & PTE_USER))
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#ifdef CONFIG_ARM64_HW_AFDBM
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#define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY))
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#else
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#define pte_hw_dirty(pte) (0)
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#endif
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#define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY))
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#define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte))
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#define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID))
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#define pte_valid_not_user(pte) \
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((pte_val(pte) & (PTE_VALID | PTE_USER)) == PTE_VALID)
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#define pte_valid_young(pte) \
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((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF))
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/*
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* Could the pte be present in the TLB? We must check mm_tlb_flush_pending
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* so that we don't erroneously return false for pages that have been
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* remapped as PROT_NONE but are yet to be flushed from the TLB.
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*/
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#define pte_accessible(mm, pte) \
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(mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte))
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static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
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{
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pte_val(pte) &= ~pgprot_val(prot);
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return pte;
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}
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static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
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{
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pte_val(pte) |= pgprot_val(prot);
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return pte;
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}
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static inline pte_t pte_wrprotect(pte_t pte)
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{
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return clear_pte_bit(pte, __pgprot(PTE_WRITE));
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}
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static inline pte_t pte_mkwrite(pte_t pte)
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{
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return set_pte_bit(pte, __pgprot(PTE_WRITE));
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}
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static inline pte_t pte_mkclean(pte_t pte)
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{
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return clear_pte_bit(pte, __pgprot(PTE_DIRTY));
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}
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static inline pte_t pte_mkdirty(pte_t pte)
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{
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return set_pte_bit(pte, __pgprot(PTE_DIRTY));
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}
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static inline pte_t pte_mkold(pte_t pte)
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{
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return clear_pte_bit(pte, __pgprot(PTE_AF));
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}
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static inline pte_t pte_mkyoung(pte_t pte)
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{
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return set_pte_bit(pte, __pgprot(PTE_AF));
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}
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static inline pte_t pte_mkspecial(pte_t pte)
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{
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return set_pte_bit(pte, __pgprot(PTE_SPECIAL));
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}
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static inline pte_t pte_mkcont(pte_t pte)
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{
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pte = set_pte_bit(pte, __pgprot(PTE_CONT));
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return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE));
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}
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static inline pte_t pte_mknoncont(pte_t pte)
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{
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return clear_pte_bit(pte, __pgprot(PTE_CONT));
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}
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static inline pmd_t pmd_mkcont(pmd_t pmd)
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{
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return __pmd(pmd_val(pmd) | PMD_SECT_CONT);
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}
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static inline void set_pte(pte_t *ptep, pte_t pte)
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{
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*ptep = pte;
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/*
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* Only if the new pte is valid and kernel, otherwise TLB maintenance
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* or update_mmu_cache() have the necessary barriers.
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*/
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if (pte_valid_not_user(pte)) {
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dsb(ishst);
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isb();
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}
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}
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struct mm_struct;
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struct vm_area_struct;
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extern void __sync_icache_dcache(pte_t pteval, unsigned long addr);
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/*
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* PTE bits configuration in the presence of hardware Dirty Bit Management
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* (PTE_WRITE == PTE_DBM):
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*
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* Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw)
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* 0 0 | 1 0 0
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* 0 1 | 1 1 0
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* 1 0 | 1 0 1
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* 1 1 | 0 1 x
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*
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* When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via
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* the page fault mechanism. Checking the dirty status of a pte becomes:
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*
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* PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY)
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*/
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static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte)
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{
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if (pte_valid(pte)) {
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if (pte_sw_dirty(pte) && pte_write(pte))
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pte_val(pte) &= ~PTE_RDONLY;
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else
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pte_val(pte) |= PTE_RDONLY;
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if (pte_user(pte) && pte_exec(pte) && !pte_special(pte))
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__sync_icache_dcache(pte, addr);
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}
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/*
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* If the existing pte is valid, check for potential race with
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* hardware updates of the pte (ptep_set_access_flags safely changes
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* valid ptes without going through an invalid entry).
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*/
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if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) &&
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pte_valid(*ptep) && pte_valid(pte)) {
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VM_WARN_ONCE(!pte_young(pte),
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"%s: racy access flag clearing: 0x%016llx -> 0x%016llx",
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__func__, pte_val(*ptep), pte_val(pte));
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VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(pte),
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"%s: racy dirty state clearing: 0x%016llx -> 0x%016llx",
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__func__, pte_val(*ptep), pte_val(pte));
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}
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set_pte(ptep, pte);
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}
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/*
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* Huge pte definitions.
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*/
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#define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT))
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#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
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/*
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* Hugetlb definitions.
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*/
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#define HUGE_MAX_HSTATE 4
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#define HPAGE_SHIFT PMD_SHIFT
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#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
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#define HPAGE_MASK (~(HPAGE_SIZE - 1))
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#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
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#define __HAVE_ARCH_PTE_SPECIAL
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static inline pte_t pud_pte(pud_t pud)
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{
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return __pte(pud_val(pud));
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}
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static inline pmd_t pud_pmd(pud_t pud)
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{
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return __pmd(pud_val(pud));
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}
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static inline pte_t pmd_pte(pmd_t pmd)
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{
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return __pte(pmd_val(pmd));
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}
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static inline pmd_t pte_pmd(pte_t pte)
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{
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return __pmd(pte_val(pte));
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}
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static inline pgprot_t mk_sect_prot(pgprot_t prot)
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{
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return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT);
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}
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/*
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* THP definitions.
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*/
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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#define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
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#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
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#define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd))
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#define pmd_young(pmd) pte_young(pmd_pte(pmd))
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#define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd)))
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#define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd)))
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#define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd)))
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#define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd)))
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#define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd)))
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#define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd)))
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#define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_TYPE_MASK))
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#define __HAVE_ARCH_PMD_WRITE
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#define pmd_write(pmd) pte_write(pmd_pte(pmd))
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#define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
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#define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
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#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
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#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
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#define pud_write(pud) pte_write(pud_pte(pud))
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#define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
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#define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd))
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static inline int has_transparent_hugepage(void)
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{
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return 1;
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}
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#define __pgprot_modify(prot,mask,bits) \
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__pgprot((pgprot_val(prot) & ~(mask)) | (bits))
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/*
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* Mark the prot value as uncacheable and unbufferable.
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*/
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#define pgprot_noncached(prot) \
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
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#define pgprot_writecombine(prot) \
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
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#define pgprot_device(prot) \
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
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#define __HAVE_PHYS_MEM_ACCESS_PROT
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struct file;
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extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
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unsigned long size, pgprot_t vma_prot);
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#define pmd_none(pmd) (!pmd_val(pmd))
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#define pmd_present(pmd) (pmd_val(pmd))
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#define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
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#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
|
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PMD_TYPE_TABLE)
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#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
|
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PMD_TYPE_SECT)
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#ifdef CONFIG_ARM64_64K_PAGES
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#define pud_sect(pud) (0)
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#define pud_table(pud) (1)
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#else
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#define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
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PUD_TYPE_SECT)
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#define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \
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PUD_TYPE_TABLE)
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#endif
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static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
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{
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*pmdp = pmd;
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dsb(ishst);
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isb();
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}
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static inline void pmd_clear(pmd_t *pmdp)
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{
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set_pmd(pmdp, __pmd(0));
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}
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static inline pte_t *pmd_page_vaddr(pmd_t pmd)
|
|
{
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return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK);
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}
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#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
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#if CONFIG_PGTABLE_LEVELS > 2
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#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
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#define pud_none(pud) (!pud_val(pud))
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#define pud_bad(pud) (!(pud_val(pud) & 2))
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#define pud_present(pud) (pud_val(pud))
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static inline void set_pud(pud_t *pudp, pud_t pud)
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{
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*pudp = pud;
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dsb(ishst);
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isb();
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}
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static inline void pud_clear(pud_t *pudp)
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{
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set_pud(pudp, __pud(0));
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}
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static inline pmd_t *pud_page_vaddr(pud_t pud)
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|
{
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return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
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}
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/* Find an entry in the second-level page table. */
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#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
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static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
|
|
{
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return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
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}
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#define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK))
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#endif /* CONFIG_PGTABLE_LEVELS > 2 */
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#if CONFIG_PGTABLE_LEVELS > 3
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#define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
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#define pgd_none(pgd) (!pgd_val(pgd))
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#define pgd_bad(pgd) (!(pgd_val(pgd) & 2))
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#define pgd_present(pgd) (pgd_val(pgd))
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|
|
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static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
|
|
{
|
|
*pgdp = pgd;
|
|
dsb(ishst);
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|
}
|
|
|
|
static inline void pgd_clear(pgd_t *pgdp)
|
|
{
|
|
set_pgd(pgdp, __pgd(0));
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|
}
|
|
|
|
static inline pud_t *pgd_page_vaddr(pgd_t pgd)
|
|
{
|
|
return __va(pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK);
|
|
}
|
|
|
|
/* Find an entry in the frst-level page table. */
|
|
#define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
|
|
|
|
static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr)
|
|
{
|
|
return (pud_t *)pgd_page_vaddr(*pgd) + pud_index(addr);
|
|
}
|
|
|
|
#define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK))
|
|
|
|
#endif /* CONFIG_PGTABLE_LEVELS > 3 */
|
|
|
|
#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
|
|
|
|
/* to find an entry in a page-table-directory */
|
|
#define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
|
|
|
|
#define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr))
|
|
|
|
/* to find an entry in a kernel page-table-directory */
|
|
#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
|
|
|
|
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
|
{
|
|
const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
|
|
PTE_PROT_NONE | PTE_VALID | PTE_WRITE;
|
|
/* preserve the hardware dirty information */
|
|
if (pte_hw_dirty(pte))
|
|
pte = pte_mkdirty(pte);
|
|
pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
|
|
return pte;
|
|
}
|
|
|
|
static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
|
|
{
|
|
return pte_pmd(pte_modify(pmd_pte(pmd), newprot));
|
|
}
|
|
|
|
#ifdef CONFIG_ARM64_HW_AFDBM
|
|
/*
|
|
* Atomic pte/pmd modifications.
|
|
*/
|
|
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
|
|
static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
|
|
unsigned long address,
|
|
pte_t *ptep)
|
|
{
|
|
pteval_t pteval;
|
|
unsigned int tmp, res;
|
|
|
|
asm volatile("// ptep_test_and_clear_young\n"
|
|
" prfm pstl1strm, %2\n"
|
|
"1: ldxr %0, %2\n"
|
|
" ubfx %w3, %w0, %5, #1 // extract PTE_AF (young)\n"
|
|
" and %0, %0, %4 // clear PTE_AF\n"
|
|
" stxr %w1, %0, %2\n"
|
|
" cbnz %w1, 1b\n"
|
|
: "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)), "=&r" (res)
|
|
: "L" (~PTE_AF), "I" (ilog2(PTE_AF)));
|
|
|
|
return res;
|
|
}
|
|
|
|
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
|
#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
|
|
static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
|
|
unsigned long address,
|
|
pmd_t *pmdp)
|
|
{
|
|
return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp);
|
|
}
|
|
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
|
|
|
|
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
|
|
static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
|
|
unsigned long address, pte_t *ptep)
|
|
{
|
|
pteval_t old_pteval;
|
|
unsigned int tmp;
|
|
|
|
asm volatile("// ptep_get_and_clear\n"
|
|
" prfm pstl1strm, %2\n"
|
|
"1: ldxr %0, %2\n"
|
|
" stxr %w1, xzr, %2\n"
|
|
" cbnz %w1, 1b\n"
|
|
: "=&r" (old_pteval), "=&r" (tmp), "+Q" (pte_val(*ptep)));
|
|
|
|
return __pte(old_pteval);
|
|
}
|
|
|
|
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
|
#define __HAVE_ARCH_PMDP_GET_AND_CLEAR
|
|
static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
|
|
unsigned long address, pmd_t *pmdp)
|
|
{
|
|
return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp));
|
|
}
|
|
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
|
|
|
|
/*
|
|
* ptep_set_wrprotect - mark read-only while trasferring potential hardware
|
|
* dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit.
|
|
*/
|
|
#define __HAVE_ARCH_PTEP_SET_WRPROTECT
|
|
static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
|
|
{
|
|
pteval_t pteval;
|
|
unsigned long tmp;
|
|
|
|
asm volatile("// ptep_set_wrprotect\n"
|
|
" prfm pstl1strm, %2\n"
|
|
"1: ldxr %0, %2\n"
|
|
" tst %0, %4 // check for hw dirty (!PTE_RDONLY)\n"
|
|
" csel %1, %3, xzr, eq // set PTE_DIRTY|PTE_RDONLY if dirty\n"
|
|
" orr %0, %0, %1 // if !dirty, PTE_RDONLY is already set\n"
|
|
" and %0, %0, %5 // clear PTE_WRITE/PTE_DBM\n"
|
|
" stxr %w1, %0, %2\n"
|
|
" cbnz %w1, 1b\n"
|
|
: "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*ptep))
|
|
: "r" (PTE_DIRTY|PTE_RDONLY), "L" (PTE_RDONLY), "L" (~PTE_WRITE)
|
|
: "cc");
|
|
}
|
|
|
|
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
|
|
#define __HAVE_ARCH_PMDP_SET_WRPROTECT
|
|
static inline void pmdp_set_wrprotect(struct mm_struct *mm,
|
|
unsigned long address, pmd_t *pmdp)
|
|
{
|
|
ptep_set_wrprotect(mm, address, (pte_t *)pmdp);
|
|
}
|
|
#endif
|
|
#endif /* CONFIG_ARM64_HW_AFDBM */
|
|
|
|
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
|
|
extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
|
|
|
|
/*
|
|
* Encode and decode a swap entry:
|
|
* bits 0-1: present (must be zero)
|
|
* bits 2-7: swap type
|
|
* bits 8-57: swap offset
|
|
*/
|
|
#define __SWP_TYPE_SHIFT 2
|
|
#define __SWP_TYPE_BITS 6
|
|
#define __SWP_OFFSET_BITS 50
|
|
#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
|
|
#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
|
|
#define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
|
|
|
|
#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
|
|
#define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK)
|
|
#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })
|
|
|
|
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
|
|
#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
|
|
|
|
/*
|
|
* Ensure that there are not more swap files than can be encoded in the kernel
|
|
* PTEs.
|
|
*/
|
|
#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
|
|
|
|
extern int kern_addr_valid(unsigned long addr);
|
|
|
|
#include <asm-generic/pgtable.h>
|
|
|
|
void pgd_cache_init(void);
|
|
#define pgtable_cache_init pgd_cache_init
|
|
|
|
/*
|
|
* On AArch64, the cache coherency is handled via the set_pte_at() function.
|
|
*/
|
|
static inline void update_mmu_cache(struct vm_area_struct *vma,
|
|
unsigned long addr, pte_t *ptep)
|
|
{
|
|
/*
|
|
* We don't do anything here, so there's a very small chance of
|
|
* us retaking a user fault which we just fixed up. The alternative
|
|
* is doing a dsb(ishst), but that penalises the fastpath.
|
|
*/
|
|
}
|
|
|
|
#define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)
|
|
|
|
#define kc_vaddr_to_offset(v) ((v) & ~VA_START)
|
|
#define kc_offset_to_vaddr(o) ((o) | VA_START)
|
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
|
|
#endif /* __ASM_PGTABLE_H */
|