371 lines
9.7 KiB
C
371 lines
9.7 KiB
C
/*
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* HDMI driver definition for TI OMAP4 Processor.
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _HDMI_H
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#define _HDMI_H
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/hdmi.h>
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#include <sound/omap-hdmi-audio.h>
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#include "omapdss.h"
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#include "dss.h"
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/* HDMI Wrapper */
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#define HDMI_WP_REVISION 0x0
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#define HDMI_WP_SYSCONFIG 0x10
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#define HDMI_WP_IRQSTATUS_RAW 0x24
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#define HDMI_WP_IRQSTATUS 0x28
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#define HDMI_WP_IRQENABLE_SET 0x2C
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#define HDMI_WP_IRQENABLE_CLR 0x30
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#define HDMI_WP_IRQWAKEEN 0x34
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#define HDMI_WP_PWR_CTRL 0x40
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#define HDMI_WP_DEBOUNCE 0x44
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#define HDMI_WP_VIDEO_CFG 0x50
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#define HDMI_WP_VIDEO_SIZE 0x60
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#define HDMI_WP_VIDEO_TIMING_H 0x68
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#define HDMI_WP_VIDEO_TIMING_V 0x6C
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#define HDMI_WP_CLK 0x70
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#define HDMI_WP_AUDIO_CFG 0x80
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#define HDMI_WP_AUDIO_CFG2 0x84
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#define HDMI_WP_AUDIO_CTRL 0x88
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#define HDMI_WP_AUDIO_DATA 0x8C
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/* HDMI WP IRQ flags */
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#define HDMI_IRQ_CORE (1 << 0)
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#define HDMI_IRQ_OCP_TIMEOUT (1 << 4)
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#define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW (1 << 8)
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#define HDMI_IRQ_AUDIO_FIFO_OVERFLOW (1 << 9)
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#define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ (1 << 10)
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#define HDMI_IRQ_VIDEO_VSYNC (1 << 16)
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#define HDMI_IRQ_VIDEO_FRAME_DONE (1 << 17)
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#define HDMI_IRQ_PHY_LINE5V_ASSERT (1 << 24)
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#define HDMI_IRQ_LINK_CONNECT (1 << 25)
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#define HDMI_IRQ_LINK_DISCONNECT (1 << 26)
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#define HDMI_IRQ_PLL_LOCK (1 << 29)
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#define HDMI_IRQ_PLL_UNLOCK (1 << 30)
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#define HDMI_IRQ_PLL_RECAL (1 << 31)
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/* HDMI PLL */
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#define PLLCTRL_PLL_CONTROL 0x0
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#define PLLCTRL_PLL_STATUS 0x4
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#define PLLCTRL_PLL_GO 0x8
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#define PLLCTRL_CFG1 0xC
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#define PLLCTRL_CFG2 0x10
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#define PLLCTRL_CFG3 0x14
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#define PLLCTRL_SSC_CFG1 0x18
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#define PLLCTRL_SSC_CFG2 0x1C
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#define PLLCTRL_CFG4 0x20
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/* HDMI PHY */
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#define HDMI_TXPHY_TX_CTRL 0x0
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#define HDMI_TXPHY_DIGITAL_CTRL 0x4
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#define HDMI_TXPHY_POWER_CTRL 0x8
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#define HDMI_TXPHY_PAD_CFG_CTRL 0xC
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#define HDMI_TXPHY_BIST_CONTROL 0x1C
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enum hdmi_pll_pwr {
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HDMI_PLLPWRCMD_ALLOFF = 0,
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HDMI_PLLPWRCMD_PLLONLY = 1,
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HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
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HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
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};
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enum hdmi_phy_pwr {
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HDMI_PHYPWRCMD_OFF = 0,
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HDMI_PHYPWRCMD_LDOON = 1,
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HDMI_PHYPWRCMD_TXON = 2
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};
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enum hdmi_core_hdmi_dvi {
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HDMI_DVI = 0,
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HDMI_HDMI = 1
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};
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enum hdmi_packing_mode {
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HDMI_PACK_10b_RGB_YUV444 = 0,
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HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
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HDMI_PACK_20b_YUV422 = 2,
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HDMI_PACK_ALREADYPACKED = 7
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};
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enum hdmi_stereo_channels {
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HDMI_AUDIO_STEREO_NOCHANNELS = 0,
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HDMI_AUDIO_STEREO_ONECHANNEL = 1,
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HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
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HDMI_AUDIO_STEREO_THREECHANNELS = 3,
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HDMI_AUDIO_STEREO_FOURCHANNELS = 4
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};
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enum hdmi_audio_type {
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HDMI_AUDIO_TYPE_LPCM = 0,
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HDMI_AUDIO_TYPE_IEC = 1
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};
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enum hdmi_audio_justify {
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HDMI_AUDIO_JUSTIFY_LEFT = 0,
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HDMI_AUDIO_JUSTIFY_RIGHT = 1
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};
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enum hdmi_audio_sample_order {
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HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
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HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
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};
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enum hdmi_audio_samples_perword {
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HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
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HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
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};
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enum hdmi_audio_sample_size_omap {
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HDMI_AUDIO_SAMPLE_16BITS = 0,
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HDMI_AUDIO_SAMPLE_24BITS = 1
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};
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enum hdmi_audio_transf_mode {
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HDMI_AUDIO_TRANSF_DMA = 0,
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HDMI_AUDIO_TRANSF_IRQ = 1
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};
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enum hdmi_audio_blk_strt_end_sig {
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HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
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HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
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};
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enum hdmi_core_audio_layout {
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HDMI_AUDIO_LAYOUT_2CH = 0,
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HDMI_AUDIO_LAYOUT_8CH = 1,
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HDMI_AUDIO_LAYOUT_6CH = 2
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};
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enum hdmi_core_cts_mode {
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HDMI_AUDIO_CTS_MODE_HW = 0,
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HDMI_AUDIO_CTS_MODE_SW = 1
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};
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enum hdmi_audio_mclk_mode {
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HDMI_AUDIO_MCLK_128FS = 0,
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HDMI_AUDIO_MCLK_256FS = 1,
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HDMI_AUDIO_MCLK_384FS = 2,
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HDMI_AUDIO_MCLK_512FS = 3,
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HDMI_AUDIO_MCLK_768FS = 4,
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HDMI_AUDIO_MCLK_1024FS = 5,
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HDMI_AUDIO_MCLK_1152FS = 6,
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HDMI_AUDIO_MCLK_192FS = 7
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};
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struct hdmi_video_format {
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enum hdmi_packing_mode packing_mode;
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u32 y_res; /* Line per panel */
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u32 x_res; /* pixel per line */
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};
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struct hdmi_config {
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struct omap_video_timings timings;
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struct hdmi_avi_infoframe infoframe;
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enum hdmi_core_hdmi_dvi hdmi_dvi_mode;
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};
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struct hdmi_audio_format {
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enum hdmi_stereo_channels stereo_channels;
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u8 active_chnnls_msk;
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enum hdmi_audio_type type;
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enum hdmi_audio_justify justification;
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enum hdmi_audio_sample_order sample_order;
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enum hdmi_audio_samples_perword samples_per_word;
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enum hdmi_audio_sample_size_omap sample_size;
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enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end;
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};
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struct hdmi_audio_dma {
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u8 transfer_size;
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u8 block_size;
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enum hdmi_audio_transf_mode mode;
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u16 fifo_threshold;
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};
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struct hdmi_core_audio_i2s_config {
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u8 in_length_bits;
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u8 justification;
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u8 sck_edge_mode;
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u8 vbit;
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u8 direction;
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u8 shift;
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u8 active_sds;
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};
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struct hdmi_core_audio_config {
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struct hdmi_core_audio_i2s_config i2s_cfg;
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struct snd_aes_iec958 *iec60958_cfg;
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bool fs_override;
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u32 n;
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u32 cts;
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u32 aud_par_busclk;
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enum hdmi_core_audio_layout layout;
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enum hdmi_core_cts_mode cts_mode;
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bool use_mclk;
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enum hdmi_audio_mclk_mode mclk_mode;
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bool en_acr_pkt;
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bool en_dsd_audio;
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bool en_parallel_aud_input;
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bool en_spdif;
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};
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struct hdmi_wp_data {
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void __iomem *base;
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phys_addr_t phys_base;
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};
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struct hdmi_pll_data {
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struct dss_pll pll;
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void __iomem *base;
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struct platform_device *pdev;
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struct hdmi_wp_data *wp;
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};
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struct hdmi_phy_data {
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void __iomem *base;
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u8 lane_function[4];
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u8 lane_polarity[4];
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};
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struct hdmi_core_data {
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void __iomem *base;
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};
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static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
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u32 val)
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{
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__raw_writel(val, base_addr + idx);
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}
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static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx)
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{
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return __raw_readl(base_addr + idx);
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}
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#define REG_FLD_MOD(base, idx, val, start, end) \
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hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
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val, start, end))
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#define REG_GET(base, idx, start, end) \
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FLD_GET(hdmi_read_reg(base, idx), start, end)
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static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
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const u32 idx, int b2, int b1, u32 val)
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{
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u32 t = 0, v;
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while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
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if (t++ > 10000)
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return v;
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udelay(1);
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}
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return v;
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}
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/* HDMI wrapper funcs */
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int hdmi_wp_video_start(struct hdmi_wp_data *wp);
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void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
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void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
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u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
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void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
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void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
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void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
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int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
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int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
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void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
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struct hdmi_video_format *video_fmt);
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void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
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struct omap_video_timings *timings);
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void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
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struct omap_video_timings *timings);
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void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
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struct omap_video_timings *timings, struct hdmi_config *param);
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int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
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phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);
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/* HDMI PLL funcs */
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void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
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int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
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struct hdmi_wp_data *wp);
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void hdmi_pll_uninit(struct hdmi_pll_data *hpll);
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/* HDMI PHY funcs */
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int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
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unsigned long lfbitclk);
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void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
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int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy);
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int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes);
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/* HDMI common funcs */
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int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep,
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struct hdmi_phy_data *phy);
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/* Audio funcs */
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int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts);
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int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
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int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
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void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
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struct hdmi_audio_format *aud_fmt);
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void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
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struct hdmi_audio_dma *aud_dma);
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static inline bool hdmi_mode_has_audio(struct hdmi_config *cfg)
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{
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return cfg->hdmi_dvi_mode == HDMI_HDMI ? true : false;
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}
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/* HDMI DRV data */
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struct omap_hdmi {
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struct mutex lock;
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struct platform_device *pdev;
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struct hdmi_wp_data wp;
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struct hdmi_pll_data pll;
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struct hdmi_phy_data phy;
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struct hdmi_core_data core;
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struct hdmi_config cfg;
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struct regulator *vdda_reg;
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bool core_enabled;
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struct omap_dss_device output;
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struct platform_device *audio_pdev;
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void (*audio_abort_cb)(struct device *dev);
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int wp_idlemode;
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bool audio_configured;
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struct omap_dss_audio audio_config;
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/* This lock should be taken when booleans bellow are touched. */
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spinlock_t audio_playing_lock;
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bool audio_playing;
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bool display_enabled;
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};
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#endif
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