255 lines
6.7 KiB
C
255 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Fault injection for both 32 and 64bit guests.
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*
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* Copyright (C) 2012,2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Based on arch/arm/kvm/emulate.c
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University
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* Author: Christoffer Dall <c.dall@virtualopensystems.com>
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*/
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#include <linux/kvm_host.h>
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#include <asm/kvm_emulate.h>
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#include <asm/kvm_nested.h>
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#include <asm/esr.h>
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static void pend_sync_exception(struct kvm_vcpu *vcpu)
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{
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/* If not nesting, EL1 is the only possible exception target */
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if (likely(!vcpu_has_nv(vcpu))) {
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kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC);
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return;
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}
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/*
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* With NV, we need to pick between EL1 and EL2. Note that we
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* never deal with a nesting exception here, hence never
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* changing context, and the exception itself can be delayed
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* until the next entry.
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*/
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switch(*vcpu_cpsr(vcpu) & PSR_MODE_MASK) {
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case PSR_MODE_EL2h:
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case PSR_MODE_EL2t:
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kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_SYNC);
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break;
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case PSR_MODE_EL1h:
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case PSR_MODE_EL1t:
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kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC);
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break;
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case PSR_MODE_EL0t:
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if (vcpu_el2_tge_is_set(vcpu))
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kvm_pend_exception(vcpu, EXCEPT_AA64_EL2_SYNC);
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else
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kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC);
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break;
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default:
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BUG();
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}
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}
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static bool match_target_el(struct kvm_vcpu *vcpu, unsigned long target)
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{
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return (vcpu_get_flag(vcpu, EXCEPT_MASK) == target);
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}
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static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
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{
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unsigned long cpsr = *vcpu_cpsr(vcpu);
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bool is_aarch32 = vcpu_mode_is_32bit(vcpu);
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u64 esr = 0;
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pend_sync_exception(vcpu);
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/*
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* Build an {i,d}abort, depending on the level and the
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* instruction set. Report an external synchronous abort.
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*/
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if (kvm_vcpu_trap_il_is32bit(vcpu))
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esr |= ESR_ELx_IL;
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/*
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* Here, the guest runs in AArch64 mode when in EL1. If we get
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* an AArch32 fault, it means we managed to trap an EL0 fault.
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*/
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if (is_aarch32 || (cpsr & PSR_MODE_MASK) == PSR_MODE_EL0t)
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esr |= (ESR_ELx_EC_IABT_LOW << ESR_ELx_EC_SHIFT);
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else
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esr |= (ESR_ELx_EC_IABT_CUR << ESR_ELx_EC_SHIFT);
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if (!is_iabt)
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esr |= ESR_ELx_EC_DABT_LOW << ESR_ELx_EC_SHIFT;
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esr |= ESR_ELx_FSC_EXTABT;
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if (match_target_el(vcpu, unpack_vcpu_flag(EXCEPT_AA64_EL1_SYNC))) {
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vcpu_write_sys_reg(vcpu, addr, FAR_EL1);
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vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
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} else {
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vcpu_write_sys_reg(vcpu, addr, FAR_EL2);
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vcpu_write_sys_reg(vcpu, esr, ESR_EL2);
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}
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}
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static void inject_undef64(struct kvm_vcpu *vcpu)
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{
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u64 esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT);
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pend_sync_exception(vcpu);
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/*
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* Build an unknown exception, depending on the instruction
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* set.
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*/
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if (kvm_vcpu_trap_il_is32bit(vcpu))
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esr |= ESR_ELx_IL;
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if (match_target_el(vcpu, unpack_vcpu_flag(EXCEPT_AA64_EL1_SYNC)))
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vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
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else
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vcpu_write_sys_reg(vcpu, esr, ESR_EL2);
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}
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#define DFSR_FSC_EXTABT_LPAE 0x10
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#define DFSR_FSC_EXTABT_nLPAE 0x08
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#define DFSR_LPAE BIT(9)
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#define TTBCR_EAE BIT(31)
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static void inject_undef32(struct kvm_vcpu *vcpu)
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{
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kvm_pend_exception(vcpu, EXCEPT_AA32_UND);
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}
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/*
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* Modelled after TakeDataAbortException() and TakePrefetchAbortException
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* pseudocode.
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*/
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static void inject_abt32(struct kvm_vcpu *vcpu, bool is_pabt, u32 addr)
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{
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u64 far;
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u32 fsr;
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/* Give the guest an IMPLEMENTATION DEFINED exception */
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if (vcpu_read_sys_reg(vcpu, TCR_EL1) & TTBCR_EAE) {
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fsr = DFSR_LPAE | DFSR_FSC_EXTABT_LPAE;
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} else {
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/* no need to shuffle FS[4] into DFSR[10] as its 0 */
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fsr = DFSR_FSC_EXTABT_nLPAE;
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}
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far = vcpu_read_sys_reg(vcpu, FAR_EL1);
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if (is_pabt) {
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kvm_pend_exception(vcpu, EXCEPT_AA32_IABT);
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far &= GENMASK(31, 0);
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far |= (u64)addr << 32;
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vcpu_write_sys_reg(vcpu, fsr, IFSR32_EL2);
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} else { /* !iabt */
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kvm_pend_exception(vcpu, EXCEPT_AA32_DABT);
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far &= GENMASK(63, 32);
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far |= addr;
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vcpu_write_sys_reg(vcpu, fsr, ESR_EL1);
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}
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vcpu_write_sys_reg(vcpu, far, FAR_EL1);
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}
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/**
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* kvm_inject_dabt - inject a data abort into the guest
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* @vcpu: The VCPU to receive the data abort
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* @addr: The address to report in the DFAR
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*/
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void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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if (vcpu_el1_is_32bit(vcpu))
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inject_abt32(vcpu, false, addr);
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else
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inject_abt64(vcpu, false, addr);
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}
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/**
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* kvm_inject_pabt - inject a prefetch abort into the guest
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* @vcpu: The VCPU to receive the prefetch abort
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* @addr: The address to report in the DFAR
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*/
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void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
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{
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if (vcpu_el1_is_32bit(vcpu))
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inject_abt32(vcpu, true, addr);
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else
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inject_abt64(vcpu, true, addr);
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}
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void kvm_inject_size_fault(struct kvm_vcpu *vcpu)
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{
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unsigned long addr, esr;
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addr = kvm_vcpu_get_fault_ipa(vcpu);
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addr |= kvm_vcpu_get_hfar(vcpu) & GENMASK(11, 0);
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if (kvm_vcpu_trap_is_iabt(vcpu))
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kvm_inject_pabt(vcpu, addr);
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else
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kvm_inject_dabt(vcpu, addr);
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/*
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* If AArch64 or LPAE, set FSC to 0 to indicate an Address
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* Size Fault at level 0, as if exceeding PARange.
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*
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* Non-LPAE guests will only get the external abort, as there
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* is no way to to describe the ASF.
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*/
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if (vcpu_el1_is_32bit(vcpu) &&
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!(vcpu_read_sys_reg(vcpu, TCR_EL1) & TTBCR_EAE))
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return;
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esr = vcpu_read_sys_reg(vcpu, ESR_EL1);
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esr &= ~GENMASK_ULL(5, 0);
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vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
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}
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/**
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* kvm_inject_undefined - inject an undefined instruction into the guest
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* @vcpu: The vCPU in which to inject the exception
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*/
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void kvm_inject_undefined(struct kvm_vcpu *vcpu)
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{
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if (vcpu_el1_is_32bit(vcpu))
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inject_undef32(vcpu);
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else
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inject_undef64(vcpu);
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}
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void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 esr)
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{
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vcpu_set_vsesr(vcpu, esr & ESR_ELx_ISS_MASK);
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*vcpu_hcr(vcpu) |= HCR_VSE;
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}
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/**
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* kvm_inject_vabt - inject an async abort / SError into the guest
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* @vcpu: The VCPU to receive the exception
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*
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* It is assumed that this code is called from the VCPU thread and that the
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* VCPU therefore is not currently executing guest code.
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*
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* Systems with the RAS Extensions specify an imp-def ESR (ISV/IDS = 1) with
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* the remaining ISS all-zeros so that this error is not interpreted as an
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* uncategorized RAS error. Without the RAS Extensions we can't specify an ESR
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* value, so the CPU generates an imp-def value.
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*/
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void kvm_inject_vabt(struct kvm_vcpu *vcpu)
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{
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kvm_set_sei_esr(vcpu, ESR_ELx_ISV);
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}
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