98 lines
3.3 KiB
C
98 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 1999 - 2020 Intel Corporation. */
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#ifndef _IXGBE_DCB_82599_H_
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#define _IXGBE_DCB_82599_H_
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/* DCB register definitions */
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#define IXGBE_RTTDCS_TDPAC 0x00000001 /* 0 Round Robin,
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* 1 WSP - Weighted Strict Priority
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*/
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#define IXGBE_RTTDCS_VMPAC 0x00000002 /* 0 Round Robin,
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* 1 WRR - Weighted Round Robin
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*/
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#define IXGBE_RTTDCS_TDRM 0x00000010 /* Transmit Recycle Mode */
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#define IXGBE_RTTDCS_BDPM 0x00400000 /* Bypass Data Pipe - must clear! */
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#define IXGBE_RTTDCS_BPBFSM 0x00800000 /* Bypass PB Free Space - must
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* clear!
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*/
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#define IXGBE_RTTDCS_SPEED_CHG 0x80000000 /* Link speed change */
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/* Receive UP2TC mapping */
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#define IXGBE_RTRUP2TC_UP_SHIFT 3
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#define IXGBE_RTRUP2TC_UP_MASK 7
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/* Transmit UP2TC mapping */
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#define IXGBE_RTTUP2TC_UP_SHIFT 3
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#define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */
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#define IXGBE_RTRPT4C_BWG_SHIFT 9 /* Offset to BWG index */
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#define IXGBE_RTRPT4C_GSP 0x40000000 /* GSP enable bit */
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#define IXGBE_RTRPT4C_LSP 0x80000000 /* LSP enable bit */
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#define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet
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* buffers enable
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*/
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#define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores
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* (RSS) enable
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*/
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/* RTRPCS Bit Masks */
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#define IXGBE_RTRPCS_RRM 0x00000002 /* Receive Recycle Mode enable */
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/* Receive Arbitration Control: 0 Round Robin, 1 DFP */
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#define IXGBE_RTRPCS_RAC 0x00000004
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#define IXGBE_RTRPCS_ARBDIS 0x00000040 /* Arbitration disable bit */
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/* RTTDT2C Bit Masks */
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#define IXGBE_RTTDT2C_MCL_SHIFT 12
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#define IXGBE_RTTDT2C_BWG_SHIFT 9
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#define IXGBE_RTTDT2C_GSP 0x40000000
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#define IXGBE_RTTDT2C_LSP 0x80000000
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#define IXGBE_RTTPT2C_MCL_SHIFT 12
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#define IXGBE_RTTPT2C_BWG_SHIFT 9
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#define IXGBE_RTTPT2C_GSP 0x40000000
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#define IXGBE_RTTPT2C_LSP 0x80000000
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/* RTTPCS Bit Masks */
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#define IXGBE_RTTPCS_TPPAC 0x00000020 /* 0 Round Robin,
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* 1 SP - Strict Priority
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*/
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#define IXGBE_RTTPCS_ARBDIS 0x00000040 /* Arbiter disable */
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#define IXGBE_RTTPCS_TPRM 0x00000100 /* Transmit Recycle Mode enable */
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#define IXGBE_RTTPCS_ARBD_SHIFT 22
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#define IXGBE_RTTPCS_ARBD_DCB 0x4 /* Arbitration delay in DCB mode */
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#define IXGBE_TXPBTHRESH_DCB 0xA /* THRESH value for DCB mode */
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/* SECTXMINIFG DCB */
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#define IXGBE_SECTX_DCB 0x00001F00 /* DCB TX Buffer SEC IFG */
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/* DCB driver APIs */
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/* DCB PFC */
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s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *, u8, u8 *);
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/* DCB stats */
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s32 ixgbe_dcb_config_tc_stats_82599(struct ixgbe_hw *,
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struct ixgbe_dcb_config *);
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s32 ixgbe_dcb_get_tc_stats_82599(struct ixgbe_hw *,
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struct ixgbe_hw_stats *, u8);
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s32 ixgbe_dcb_get_pfc_stats_82599(struct ixgbe_hw *,
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struct ixgbe_hw_stats *, u8);
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/* DCB config arbiters */
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s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *,
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u8 *, u8 *);
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s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *,
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u8 *, u8 *, u8 *);
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s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *, u16 *, u16 *, u8 *,
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u8 *, u8 *);
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/* DCB initialization */
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s32 ixgbe_dcb_config_82599(struct ixgbe_hw *,
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struct ixgbe_dcb_config *);
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s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *, int, u16 *, u16 *, u8 *,
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u8 *, u8 *);
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#endif /* _IXGBE_DCB_82959_H_ */
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