41 lines
1.3 KiB
Plaintext
41 lines
1.3 KiB
Plaintext
* Freescale 83xx and 512x PCI bridges
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Freescale 83xx and 512x SOCs include the same pci bridge core.
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83xx/512x specific notes:
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- reg: should contain two address length tuples
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The first is for the internal pci bridge registers
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The second is for the pci config space access registers
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Example (MPC8313ERDB)
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pci0: pci@e0008500 {
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cell-index = <1>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x0E -mini PCI */
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0x7000 0x0 0x0 0x1 &ipic 18 0x8
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0x7000 0x0 0x0 0x2 &ipic 18 0x8
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0x7000 0x0 0x0 0x3 &ipic 18 0x8
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0x7000 0x0 0x0 0x4 &ipic 18 0x8
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/* IDSEL 0x0F - PCI slot */
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0x7800 0x0 0x0 0x1 &ipic 17 0x8
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0x7800 0x0 0x0 0x2 &ipic 18 0x8
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0x7800 0x0 0x0 0x3 &ipic 17 0x8
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0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
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interrupt-parent = <&ipic>;
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interrupts = <66 0x8>;
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bus-range = <0x0 0x0>;
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ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
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0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
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clock-frequency = <66666666>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008500 0x100 /* internal registers */
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0xe0008300 0x8>; /* config space access registers */
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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