662 lines
15 KiB
Plaintext
662 lines
15 KiB
Plaintext
/*
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* P4080 Silicon Device Tree Source
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*
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* Copyright 2009-2011 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/dts-v1/;
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/ {
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compatible = "fsl,P4080";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases {
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ccsr = &soc;
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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pci0 = &pci0;
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pci1 = &pci1;
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pci2 = &pci2;
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usb0 = &usb0;
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usb1 = &usb1;
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dma0 = &dma0;
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dma1 = &dma1;
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sdhc = &sdhc;
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msi0 = &msi0;
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msi1 = &msi1;
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msi2 = &msi2;
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crypto = &crypto;
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sec_jr0 = &sec_jr0;
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sec_jr1 = &sec_jr1;
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sec_jr2 = &sec_jr2;
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sec_jr3 = &sec_jr3;
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rtic_a = &rtic_a;
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rtic_b = &rtic_b;
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rtic_c = &rtic_c;
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rtic_d = &rtic_d;
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sec_mon = &sec_mon;
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rio0 = &rapidio0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: PowerPC,4080@0 {
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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cpu1: PowerPC,4080@1 {
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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cpu2: PowerPC,4080@2 {
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device_type = "cpu";
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reg = <2>;
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next-level-cache = <&L2_2>;
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L2_2: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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cpu3: PowerPC,4080@3 {
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device_type = "cpu";
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reg = <3>;
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next-level-cache = <&L2_3>;
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L2_3: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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cpu4: PowerPC,4080@4 {
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device_type = "cpu";
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reg = <4>;
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next-level-cache = <&L2_4>;
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L2_4: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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cpu5: PowerPC,4080@5 {
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device_type = "cpu";
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reg = <5>;
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next-level-cache = <&L2_5>;
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L2_5: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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cpu6: PowerPC,4080@6 {
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device_type = "cpu";
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reg = <6>;
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next-level-cache = <&L2_6>;
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L2_6: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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cpu7: PowerPC,4080@7 {
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device_type = "cpu";
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reg = <7>;
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next-level-cache = <&L2_7>;
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L2_7: l2-cache {
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next-level-cache = <&cpc>;
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};
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};
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};
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soc: soc@ffe000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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soc-sram-error {
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compatible = "fsl,soc-sram-error";
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interrupts = <16 2 1 29>;
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};
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corenet-law@0 {
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compatible = "fsl,corenet-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <32>;
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};
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memory-controller@8000 {
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compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
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reg = <0x8000 0x1000>;
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interrupts = <16 2 1 23>;
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};
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memory-controller@9000 {
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compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
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reg = <0x9000 0x1000>;
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interrupts = <16 2 1 22>;
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};
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cpc: l3-cache-controller@10000 {
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compatible = "fsl,p4080-l3-cache-controller", "cache";
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reg = <0x10000 0x1000
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0x11000 0x1000>;
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interrupts = <16 2 1 27
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16 2 1 26>;
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};
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corenet-cf@18000 {
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compatible = "fsl,corenet-cf";
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reg = <0x18000 0x1000>;
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interrupts = <16 2 1 31>;
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fsl,ccf-num-csdids = <32>;
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fsl,ccf-num-snoopids = <32>;
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};
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iommu@20000 {
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compatible = "fsl,pamu-v1.0", "fsl,pamu";
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reg = <0x20000 0x5000>;
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interrupts = <
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24 2 0 0
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16 2 1 30>;
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};
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mpic: pic@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <4>;
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reg = <0x40000 0x40000>;
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compatible = "fsl,mpic", "chrp,open-pic";
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device_type = "open-pic";
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};
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msi0: msi@41600 {
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compatible = "fsl,mpic-msi";
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reg = <0x41600 0x200>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe0 0 0 0
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0xe1 0 0 0
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0xe2 0 0 0
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0xe3 0 0 0
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0xe4 0 0 0
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0xe5 0 0 0
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0xe6 0 0 0
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0xe7 0 0 0>;
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};
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msi1: msi@41800 {
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compatible = "fsl,mpic-msi";
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reg = <0x41800 0x200>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xe8 0 0 0
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0xe9 0 0 0
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0xea 0 0 0
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0xeb 0 0 0
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0xec 0 0 0
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0xed 0 0 0
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0xee 0 0 0
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0xef 0 0 0>;
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};
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msi2: msi@41a00 {
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compatible = "fsl,mpic-msi";
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reg = <0x41a00 0x200>;
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msi-available-ranges = <0 0x100>;
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interrupts = <
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0xf0 0 0 0
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0xf1 0 0 0
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0xf2 0 0 0
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0xf3 0 0 0
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0xf4 0 0 0
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0xf5 0 0 0
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0xf6 0 0 0
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0xf7 0 0 0>;
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};
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guts: global-utilities@e0000 {
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compatible = "fsl,qoriq-device-config-1.0";
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reg = <0xe0000 0xe00>;
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fsl,has-rstcr;
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#sleep-cells = <1>;
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fsl,liodn-bits = <12>;
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};
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pins: global-utilities@e0e00 {
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compatible = "fsl,qoriq-pin-control-1.0";
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reg = <0xe0e00 0x200>;
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#sleep-cells = <2>;
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};
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clockgen: global-utilities@e1000 {
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compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
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reg = <0xe1000 0x1000>;
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clock-frequency = <0>;
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};
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rcpm: global-utilities@e2000 {
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compatible = "fsl,qoriq-rcpm-1.0";
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reg = <0xe2000 0x1000>;
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#sleep-cells = <1>;
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};
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sfp: sfp@e8000 {
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compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
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reg = <0xe8000 0x1000>;
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};
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serdes: serdes@ea000 {
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compatible = "fsl,p4080-serdes";
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reg = <0xea000 0x1000>;
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};
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dma0: dma@100300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
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reg = <0x100300 0x4>;
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ranges = <0x0 0x100100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupts = <28 2 0 0>;
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};
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dma-channel@80 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupts = <29 2 0 0>;
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};
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dma-channel@100 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupts = <30 2 0 0>;
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};
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dma-channel@180 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupts = <31 2 0 0>;
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};
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};
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dma1: dma@101300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
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reg = <0x101300 0x4>;
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ranges = <0x0 0x101100 0x200>;
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cell-index = <1>;
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dma-channel@0 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupts = <32 2 0 0>;
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};
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dma-channel@80 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupts = <33 2 0 0>;
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};
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dma-channel@100 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupts = <34 2 0 0>;
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};
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dma-channel@180 {
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compatible = "fsl,p4080-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupts = <35 2 0 0>;
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};
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};
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spi@110000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
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reg = <0x110000 0x1000>;
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interrupts = <53 0x2 0 0>;
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fsl,espi-num-chipselects = <4>;
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};
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sdhc: sdhc@114000 {
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compatible = "fsl,p4080-esdhc", "fsl,esdhc";
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reg = <0x114000 0x1000>;
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interrupts = <48 2 0 0>;
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voltage-ranges = <3300 3300>;
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sdhci,auto-cmd12;
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clock-frequency = <0>;
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};
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i2c@118000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x118000 0x100>;
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interrupts = <38 2 0 0>;
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dfsrr;
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};
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i2c@118100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x118100 0x100>;
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interrupts = <38 2 0 0>;
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dfsrr;
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};
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i2c@119000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <2>;
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compatible = "fsl-i2c";
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reg = <0x119000 0x100>;
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interrupts = <39 2 0 0>;
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dfsrr;
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};
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i2c@119100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <3>;
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compatible = "fsl-i2c";
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reg = <0x119100 0x100>;
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interrupts = <39 2 0 0>;
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dfsrr;
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};
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serial0: serial@11c500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x11c500 0x100>;
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clock-frequency = <0>;
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interrupts = <36 2 0 0>;
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};
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serial1: serial@11c600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x11c600 0x100>;
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clock-frequency = <0>;
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interrupts = <36 2 0 0>;
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};
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serial2: serial@11d500 {
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cell-index = <2>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x11d500 0x100>;
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clock-frequency = <0>;
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interrupts = <37 2 0 0>;
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};
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serial3: serial@11d600 {
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cell-index = <3>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x11d600 0x100>;
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clock-frequency = <0>;
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interrupts = <37 2 0 0>;
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};
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gpio0: gpio@130000 {
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compatible = "fsl,p4080-gpio", "fsl,qoriq-gpio";
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reg = <0x130000 0x1000>;
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interrupts = <55 2 0 0>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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usb0: usb@210000 {
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compatible = "fsl,p4080-usb2-mph",
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"fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
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reg = <0x210000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <44 0x2 0 0>;
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};
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usb1: usb@211000 {
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compatible = "fsl,p4080-usb2-dr",
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"fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
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reg = <0x211000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <45 0x2 0 0>;
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};
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crypto: crypto@300000 {
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compatible = "fsl,sec-v4.0";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x300000 0x10000>;
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ranges = <0 0x300000 0x10000>;
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interrupt-parent = <&mpic>;
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interrupts = <92 2 0 0>;
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sec_jr0: jr@1000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x1000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <88 2 0 0>;
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};
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sec_jr1: jr@2000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x2000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <89 2 0 0>;
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};
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sec_jr2: jr@3000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x3000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <90 2 0 0>;
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};
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sec_jr3: jr@4000 {
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compatible = "fsl,sec-v4.0-job-ring";
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reg = <0x4000 0x1000>;
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interrupt-parent = <&mpic>;
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interrupts = <91 2 0 0>;
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};
|
|
|
|
rtic@6000 {
|
|
compatible = "fsl,sec-v4.0-rtic";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x6000 0x100>;
|
|
ranges = <0x0 0x6100 0xe00>;
|
|
|
|
rtic_a: rtic-a@0 {
|
|
compatible = "fsl,sec-v4.0-rtic-memory";
|
|
reg = <0x00 0x20 0x100 0x80>;
|
|
};
|
|
|
|
rtic_b: rtic-b@20 {
|
|
compatible = "fsl,sec-v4.0-rtic-memory";
|
|
reg = <0x20 0x20 0x200 0x80>;
|
|
};
|
|
|
|
rtic_c: rtic-c@40 {
|
|
compatible = "fsl,sec-v4.0-rtic-memory";
|
|
reg = <0x40 0x20 0x300 0x80>;
|
|
};
|
|
|
|
rtic_d: rtic-d@60 {
|
|
compatible = "fsl,sec-v4.0-rtic-memory";
|
|
reg = <0x60 0x20 0x500 0x80>;
|
|
};
|
|
};
|
|
};
|
|
|
|
sec_mon: sec_mon@314000 {
|
|
compatible = "fsl,sec-v4.0-mon";
|
|
reg = <0x314000 0x1000>;
|
|
interrupt-parent = <&mpic>;
|
|
interrupts = <93 2 0 0>;
|
|
};
|
|
};
|
|
|
|
rapidio0: rapidio@ffe0c0000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "fsl,rapidio-delta";
|
|
interrupts = <
|
|
16 2 1 11 /* err_irq */
|
|
56 2 0 0 /* bell_outb_irq */
|
|
57 2 0 0 /* bell_inb_irq */
|
|
60 2 0 0 /* msg1_tx_irq */
|
|
61 2 0 0 /* msg1_rx_irq */
|
|
62 2 0 0 /* msg2_tx_irq */
|
|
63 2 0 0>; /* msg2_rx_irq */
|
|
};
|
|
|
|
localbus@ffe124000 {
|
|
compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
|
|
interrupts = <25 2 0 0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
};
|
|
|
|
pci0: pcie@ffe200000 {
|
|
compatible = "fsl,p4080-pcie";
|
|
device_type = "pci";
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
bus-range = <0x0 0xff>;
|
|
clock-frequency = <0x1fca055>;
|
|
fsl,msi = <&msi0>;
|
|
interrupts = <16 2 1 15>;
|
|
pcie@0 {
|
|
reg = <0 0 0 0 0>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
interrupts = <16 2 1 15>;
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0000 0 0 1 &mpic 40 1 0 0
|
|
0000 0 0 2 &mpic 1 1 0 0
|
|
0000 0 0 3 &mpic 2 1 0 0
|
|
0000 0 0 4 &mpic 3 1 0 0
|
|
>;
|
|
};
|
|
};
|
|
|
|
pci1: pcie@ffe201000 {
|
|
compatible = "fsl,p4080-pcie";
|
|
device_type = "pci";
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
bus-range = <0 0xff>;
|
|
clock-frequency = <0x1fca055>;
|
|
fsl,msi = <&msi1>;
|
|
interrupts = <16 2 1 14>;
|
|
pcie@0 {
|
|
reg = <0 0 0 0 0>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
interrupts = <16 2 1 14>;
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0000 0 0 1 &mpic 41 1 0 0
|
|
0000 0 0 2 &mpic 5 1 0 0
|
|
0000 0 0 3 &mpic 6 1 0 0
|
|
0000 0 0 4 &mpic 7 1 0 0
|
|
>;
|
|
};
|
|
};
|
|
|
|
pci2: pcie@ffe202000 {
|
|
compatible = "fsl,p4080-pcie";
|
|
device_type = "pci";
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
bus-range = <0x0 0xff>;
|
|
clock-frequency = <0x1fca055>;
|
|
fsl,msi = <&msi2>;
|
|
interrupts = <16 2 1 13>;
|
|
pcie@0 {
|
|
reg = <0 0 0 0 0>;
|
|
#interrupt-cells = <1>;
|
|
#size-cells = <2>;
|
|
#address-cells = <3>;
|
|
device_type = "pci";
|
|
interrupts = <16 2 1 13>;
|
|
interrupt-map-mask = <0xf800 0 0 7>;
|
|
interrupt-map = <
|
|
/* IDSEL 0x0 */
|
|
0000 0 0 1 &mpic 42 1 0 0
|
|
0000 0 0 2 &mpic 9 1 0 0
|
|
0000 0 0 3 &mpic 10 1 0 0
|
|
0000 0 0 4 &mpic 11 1 0 0
|
|
>;
|
|
};
|
|
};
|
|
};
|