37 lines
996 B
C
37 lines
996 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This header provides clock numbers for the ingenic,jz4725b-cgu DT binding.
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*/
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#ifndef __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__
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#define __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__
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#define JZ4725B_CLK_EXT 0
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#define JZ4725B_CLK_OSC32K 1
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#define JZ4725B_CLK_PLL 2
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#define JZ4725B_CLK_PLL_HALF 3
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#define JZ4725B_CLK_CCLK 4
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#define JZ4725B_CLK_HCLK 5
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#define JZ4725B_CLK_PCLK 6
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#define JZ4725B_CLK_MCLK 7
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#define JZ4725B_CLK_IPU 8
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#define JZ4725B_CLK_LCD 9
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#define JZ4725B_CLK_I2S 10
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#define JZ4725B_CLK_SPI 11
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#define JZ4725B_CLK_MMC_MUX 12
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#define JZ4725B_CLK_UDC 13
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#define JZ4725B_CLK_UART 14
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#define JZ4725B_CLK_DMA 15
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#define JZ4725B_CLK_ADC 16
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#define JZ4725B_CLK_I2C 17
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#define JZ4725B_CLK_AIC 18
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#define JZ4725B_CLK_MMC0 19
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#define JZ4725B_CLK_MMC1 20
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#define JZ4725B_CLK_BCH 21
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#define JZ4725B_CLK_TCU 22
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#define JZ4725B_CLK_EXT512 23
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#define JZ4725B_CLK_RTC 24
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#define JZ4725B_CLK_UDC_PHY 25
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#endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */
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