129 lines
3.9 KiB
C
129 lines
3.9 KiB
C
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2017 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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#ifndef __CVMX_SLI_DEFS_H__
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#define __CVMX_SLI_DEFS_H__
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#include <uapi/asm/bitfield.h>
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#define CVMX_SLI_PCIE_MSI_RCV CVMX_SLI_PCIE_MSI_RCV_FUNC()
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static inline uint64_t CVMX_SLI_PCIE_MSI_RCV_FUNC(void)
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{
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switch (cvmx_get_octeon_family()) {
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case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
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return 0x0000000000003CB0ull;
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case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
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case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
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if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
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return 0x0000000000003CB0ull;
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default:
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return 0x0000000000023CB0ull;
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}
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}
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union cvmx_sli_ctl_portx {
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uint64_t u64;
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struct cvmx_sli_ctl_portx_s {
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__BITFIELD_FIELD(uint64_t reserved_22_63:42,
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__BITFIELD_FIELD(uint64_t intd:1,
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__BITFIELD_FIELD(uint64_t intc:1,
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__BITFIELD_FIELD(uint64_t intb:1,
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__BITFIELD_FIELD(uint64_t inta:1,
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__BITFIELD_FIELD(uint64_t dis_port:1,
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__BITFIELD_FIELD(uint64_t waitl_com:1,
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__BITFIELD_FIELD(uint64_t intd_map:2,
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__BITFIELD_FIELD(uint64_t intc_map:2,
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__BITFIELD_FIELD(uint64_t intb_map:2,
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__BITFIELD_FIELD(uint64_t inta_map:2,
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__BITFIELD_FIELD(uint64_t ctlp_ro:1,
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__BITFIELD_FIELD(uint64_t reserved_6_6:1,
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__BITFIELD_FIELD(uint64_t ptlp_ro:1,
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__BITFIELD_FIELD(uint64_t reserved_1_4:4,
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__BITFIELD_FIELD(uint64_t wait_com:1,
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;))))))))))))))))
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} s;
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};
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union cvmx_sli_mem_access_ctl {
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uint64_t u64;
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struct cvmx_sli_mem_access_ctl_s {
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__BITFIELD_FIELD(uint64_t reserved_14_63:50,
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__BITFIELD_FIELD(uint64_t max_word:4,
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__BITFIELD_FIELD(uint64_t timer:10,
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;)))
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} s;
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};
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union cvmx_sli_s2m_portx_ctl {
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uint64_t u64;
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struct cvmx_sli_s2m_portx_ctl_s {
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__BITFIELD_FIELD(uint64_t reserved_5_63:59,
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__BITFIELD_FIELD(uint64_t wind_d:1,
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__BITFIELD_FIELD(uint64_t bar0_d:1,
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__BITFIELD_FIELD(uint64_t mrrs:3,
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;))))
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} s;
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};
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union cvmx_sli_mem_access_subidx {
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uint64_t u64;
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struct cvmx_sli_mem_access_subidx_s {
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__BITFIELD_FIELD(uint64_t reserved_43_63:21,
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__BITFIELD_FIELD(uint64_t zero:1,
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__BITFIELD_FIELD(uint64_t port:3,
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__BITFIELD_FIELD(uint64_t nmerge:1,
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__BITFIELD_FIELD(uint64_t esr:2,
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__BITFIELD_FIELD(uint64_t esw:2,
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__BITFIELD_FIELD(uint64_t wtype:2,
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__BITFIELD_FIELD(uint64_t rtype:2,
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__BITFIELD_FIELD(uint64_t ba:30,
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;)))))))))
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} s;
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struct cvmx_sli_mem_access_subidx_cn68xx {
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__BITFIELD_FIELD(uint64_t reserved_43_63:21,
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__BITFIELD_FIELD(uint64_t zero:1,
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__BITFIELD_FIELD(uint64_t port:3,
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__BITFIELD_FIELD(uint64_t nmerge:1,
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__BITFIELD_FIELD(uint64_t esr:2,
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__BITFIELD_FIELD(uint64_t esw:2,
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__BITFIELD_FIELD(uint64_t wtype:2,
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__BITFIELD_FIELD(uint64_t rtype:2,
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__BITFIELD_FIELD(uint64_t ba:28,
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__BITFIELD_FIELD(uint64_t reserved_0_1:2,
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;))))))))))
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} cn68xx;
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};
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#endif
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