455 lines
14 KiB
C
455 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* OpenRISC Linux
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* OpenRISC implementation:
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* Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
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* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
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* et al.
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*/
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/* or32 pgtable.h - macros and functions to manipulate page tables
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*
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* Based on:
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* include/asm-cris/pgtable.h
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*/
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#ifndef __ASM_OPENRISC_PGTABLE_H
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#define __ASM_OPENRISC_PGTABLE_H
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#define __ARCH_USE_5LEVEL_HACK
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#include <asm-generic/pgtable-nopmd.h>
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#ifndef __ASSEMBLY__
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#include <asm/mmu.h>
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#include <asm/fixmap.h>
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/*
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* The Linux memory management assumes a three-level page table setup. On
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* or32, we use that, but "fold" the mid level into the top-level page
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* table. Since the MMU TLB is software loaded through an interrupt, it
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* supports any page table structure, so we could have used a three-level
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* setup, but for the amounts of memory we normally use, a two-level is
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* probably more efficient.
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*
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* This file contains the functions and defines necessary to modify and use
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* the or32 page table tree.
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*/
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extern void paging_init(void);
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/* Certain architectures need to do special things when pte's
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* within a page table are directly modified. Thus, the following
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* hook is made available.
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*/
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#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
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#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
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/*
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* (pmds are folded into pgds so this doesn't get actually called,
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* but the define is needed for a generic inline function.)
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*/
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#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
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#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-2))
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* entries per page directory level: we use a two-level, so
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* we don't really have any PMD directory physically.
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* pointers are 4 bytes so we can use the page size and
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* divide it by 4 (shift by 2).
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*/
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#define PTRS_PER_PTE (1UL << (PAGE_SHIFT-2))
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#define PTRS_PER_PGD (1UL << (32-PGDIR_SHIFT))
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/* calculate how many PGD entries a user-level program can use
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* the first mappable virtual address is 0
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* (TASK_SIZE is the maximum virtual address space)
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*/
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#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
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#define FIRST_USER_ADDRESS 0UL
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/*
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* Kernels own virtual memory area.
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*/
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/*
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* The size and location of the vmalloc area are chosen so that modules
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* placed in this area aren't more than a 28-bit signed offset from any
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* kernel functions that they may need. This greatly simplifies handling
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* of the relocations for l.j and l.jal instructions as we don't need to
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* introduce any trampolines for reaching "distant" code.
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*
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* 64 MB of vmalloc area is comparable to what's available on other arches.
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*/
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#define VMALLOC_START (PAGE_OFFSET-0x04000000UL)
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#define VMALLOC_END (PAGE_OFFSET)
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#define VMALLOC_VMADDR(x) ((unsigned long)(x))
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/* Define some higher level generic page attributes.
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*
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* If you change _PAGE_CI definition be sure to change it in
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* io.h for ioremap_nocache() too.
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*/
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/*
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* An OR32 PTE looks like this:
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*
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* | 31 ... 10 | 9 | 8 ... 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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* Phys pg.num L PP Index D A WOM WBC CI CC
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*
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* L : link
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* PPI: Page protection index
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* D : Dirty
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* A : Accessed
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* WOM: Weakly ordered memory
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* WBC: Write-back cache
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* CI : Cache inhibit
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* CC : Cache coherent
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*
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* The protection bits below should correspond to the layout of the actual
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* PTE as per above
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*/
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#define _PAGE_CC 0x001 /* software: pte contains a translation */
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#define _PAGE_CI 0x002 /* cache inhibit */
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#define _PAGE_WBC 0x004 /* write back cache */
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#define _PAGE_WOM 0x008 /* weakly ordered memory */
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#define _PAGE_A 0x010 /* accessed */
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#define _PAGE_D 0x020 /* dirty */
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#define _PAGE_URE 0x040 /* user read enable */
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#define _PAGE_UWE 0x080 /* user write enable */
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#define _PAGE_SRE 0x100 /* superuser read enable */
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#define _PAGE_SWE 0x200 /* superuser write enable */
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#define _PAGE_EXEC 0x400 /* software: page is executable */
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#define _PAGE_U_SHARED 0x800 /* software: page is shared in user space */
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/* 0x001 is cache coherency bit, which should always be set to
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* 1 - for SMP (when we support it)
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* 0 - otherwise
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*
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* we just reuse this bit in software for _PAGE_PRESENT and
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* force it to 0 when loading it into TLB.
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*/
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#define _PAGE_PRESENT _PAGE_CC
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#define _PAGE_USER _PAGE_URE
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#define _PAGE_WRITE (_PAGE_UWE | _PAGE_SWE)
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#define _PAGE_DIRTY _PAGE_D
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#define _PAGE_ACCESSED _PAGE_A
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#define _PAGE_NO_CACHE _PAGE_CI
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#define _PAGE_SHARED _PAGE_U_SHARED
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#define _PAGE_READ (_PAGE_URE | _PAGE_SRE)
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#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
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#define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
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#define _PAGE_ALL (_PAGE_PRESENT | _PAGE_ACCESSED)
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#define _KERNPG_TABLE \
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(_PAGE_BASE | _PAGE_SRE | _PAGE_SWE | _PAGE_ACCESSED | _PAGE_DIRTY)
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#define PAGE_NONE __pgprot(_PAGE_ALL)
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#define PAGE_READONLY __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE)
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#define PAGE_READONLY_X __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_EXEC)
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#define PAGE_SHARED \
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__pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_UWE | _PAGE_SWE \
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| _PAGE_SHARED)
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#define PAGE_SHARED_X \
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__pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_UWE | _PAGE_SWE \
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| _PAGE_SHARED | _PAGE_EXEC)
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#define PAGE_COPY __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE)
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#define PAGE_COPY_X __pgprot(_PAGE_ALL | _PAGE_URE | _PAGE_SRE | _PAGE_EXEC)
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#define PAGE_KERNEL \
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__pgprot(_PAGE_ALL | _PAGE_SRE | _PAGE_SWE \
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| _PAGE_SHARED | _PAGE_DIRTY | _PAGE_EXEC)
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#define PAGE_KERNEL_RO \
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__pgprot(_PAGE_ALL | _PAGE_SRE \
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| _PAGE_SHARED | _PAGE_DIRTY | _PAGE_EXEC)
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#define PAGE_KERNEL_NOCACHE \
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__pgprot(_PAGE_ALL | _PAGE_SRE | _PAGE_SWE \
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| _PAGE_SHARED | _PAGE_DIRTY | _PAGE_EXEC | _PAGE_CI)
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#define __P000 PAGE_NONE
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#define __P001 PAGE_READONLY_X
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#define __P010 PAGE_COPY
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#define __P011 PAGE_COPY_X
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#define __P100 PAGE_READONLY
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#define __P101 PAGE_READONLY_X
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#define __P110 PAGE_COPY
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#define __P111 PAGE_COPY_X
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#define __S000 PAGE_NONE
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#define __S001 PAGE_READONLY_X
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#define __S010 PAGE_SHARED
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#define __S011 PAGE_SHARED_X
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#define __S100 PAGE_READONLY
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#define __S101 PAGE_READONLY_X
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#define __S110 PAGE_SHARED
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#define __S111 PAGE_SHARED_X
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/* zero page used for uninitialized stuff */
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extern unsigned long empty_zero_page[2048];
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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/* number of bits that fit into a memory pointer */
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#define BITS_PER_PTR (8*sizeof(unsigned long))
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/* to align the pointer to a pointer address */
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#define PTR_MASK (~(sizeof(void *)-1))
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/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
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/* 64-bit machines, beware! SRB. */
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#define SIZEOF_PTR_LOG2 2
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/* to find an entry in a page-table */
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#define PAGE_PTR(address) \
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((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
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/* to set the page-dir */
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#define SET_PAGE_DIR(tsk, pgdir)
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#define pte_none(x) (!pte_val(x))
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#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
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#define pte_clear(mm, addr, xp) do { pte_val(*(xp)) = 0; } while (0)
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#define pmd_none(x) (!pmd_val(x))
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#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK)) != _KERNPG_TABLE)
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#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
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#define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
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/*
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
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static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
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static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
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static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
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static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
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static inline int pte_special(pte_t pte) { return 0; }
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static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
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static inline pte_t pte_wrprotect(pte_t pte)
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{
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pte_val(pte) &= ~(_PAGE_WRITE);
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return pte;
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}
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static inline pte_t pte_rdprotect(pte_t pte)
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{
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pte_val(pte) &= ~(_PAGE_READ);
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return pte;
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}
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static inline pte_t pte_exprotect(pte_t pte)
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{
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pte_val(pte) &= ~(_PAGE_EXEC);
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return pte;
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}
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static inline pte_t pte_mkclean(pte_t pte)
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{
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pte_val(pte) &= ~(_PAGE_DIRTY);
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return pte;
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}
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static inline pte_t pte_mkold(pte_t pte)
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{
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pte_val(pte) &= ~(_PAGE_ACCESSED);
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return pte;
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}
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static inline pte_t pte_mkwrite(pte_t pte)
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{
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pte_val(pte) |= _PAGE_WRITE;
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return pte;
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}
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static inline pte_t pte_mkread(pte_t pte)
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{
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pte_val(pte) |= _PAGE_READ;
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return pte;
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}
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static inline pte_t pte_mkexec(pte_t pte)
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{
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pte_val(pte) |= _PAGE_EXEC;
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return pte;
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}
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static inline pte_t pte_mkdirty(pte_t pte)
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{
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pte_val(pte) |= _PAGE_DIRTY;
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return pte;
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}
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static inline pte_t pte_mkyoung(pte_t pte)
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{
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pte_val(pte) |= _PAGE_ACCESSED;
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return pte;
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}
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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/* What actually goes as arguments to the various functions is less than
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* obvious, but a rule of thumb is that struct page's goes as struct page *,
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* really physical DRAM addresses are unsigned long's, and DRAM "virtual"
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* addresses (the 0xc0xxxxxx's) goes as void *'s.
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*/
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static inline pte_t __mk_pte(void *page, pgprot_t pgprot)
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{
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pte_t pte;
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/* the PTE needs a physical address */
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pte_val(pte) = __pa(page) | pgprot_val(pgprot);
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return pte;
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}
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#define mk_pte(page, pgprot) __mk_pte(page_address(page), (pgprot))
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#define mk_pte_phys(physpage, pgprot) \
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({ \
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pte_t __pte; \
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\
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pte_val(__pte) = (physpage) + pgprot_val(pgprot); \
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__pte; \
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})
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
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return pte;
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}
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/*
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* pte_val refers to a page in the 0x0xxxxxxx physical DRAM interval
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* __pte_page(pte_val) refers to the "virtual" DRAM interval
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* pte_pagenr refers to the page-number counted starting from the virtual
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* DRAM start
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*/
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static inline unsigned long __pte_page(pte_t pte)
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{
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/* the PTE contains a physical address */
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return (unsigned long)__va(pte_val(pte) & PAGE_MASK);
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}
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#define pte_pagenr(pte) ((__pte_page(pte) - PAGE_OFFSET) >> PAGE_SHIFT)
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/* permanent address of a page */
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#define __page_address(page) (PAGE_OFFSET + (((page) - mem_map) << PAGE_SHIFT))
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#define pte_page(pte) (mem_map+pte_pagenr(pte))
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/*
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* only the pte's themselves need to point to physical DRAM (see above)
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* the pagetable links are purely handled within the kernel SW and thus
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* don't need the __pa and __va transformations.
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*/
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static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
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{
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pmd_val(*pmdp) = _KERNPG_TABLE | (unsigned long) ptep;
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}
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#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
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#define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
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/* to find an entry in a page-table-directory. */
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#define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
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#define __pgd_offset(address) pgd_index(address)
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#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
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/* to find an entry in a kernel page-table-directory */
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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#define __pmd_offset(address) \
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(((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
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/*
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* the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
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*
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* this macro returns the index of the entry in the pte page which would
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* control the given virtual address
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*/
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#define __pte_offset(address) \
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(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_offset_kernel(dir, address) \
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((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(address))
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#define pte_offset_map(dir, address) \
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((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
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#define pte_offset_map_nested(dir, address) \
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pte_offset_map(dir, address)
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#define pte_unmap(pte) do { } while (0)
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#define pte_unmap_nested(pte) do { } while (0)
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#define pte_pfn(x) ((unsigned long)(((x).pte)) >> PAGE_SHIFT)
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#define pfn_pte(pfn, prot) __pte((((pfn) << PAGE_SHIFT)) | pgprot_val(prot))
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#define pte_ERROR(e) \
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printk(KERN_ERR "%s:%d: bad pte %p(%08lx).\n", \
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__FILE__, __LINE__, &(e), pte_val(e))
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#define pgd_ERROR(e) \
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printk(KERN_ERR "%s:%d: bad pgd %p(%08lx).\n", \
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__FILE__, __LINE__, &(e), pgd_val(e))
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extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
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struct vm_area_struct;
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static inline void update_tlb(struct vm_area_struct *vma,
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unsigned long address, pte_t *pte)
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{
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}
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extern void update_cache(struct vm_area_struct *vma,
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unsigned long address, pte_t *pte);
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static inline void update_mmu_cache(struct vm_area_struct *vma,
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unsigned long address, pte_t *pte)
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{
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update_tlb(vma, address, pte);
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update_cache(vma, address, pte);
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}
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/* __PHX__ FIXME, SWAP, this probably doesn't work */
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/* Encode and de-code a swap entry (must be !pte_none(e) && !pte_present(e)) */
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/* Since the PAGE_PRESENT bit is bit 4, we can use the bits above */
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#define __swp_type(x) (((x).val >> 5) & 0x7f)
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#define __swp_offset(x) ((x).val >> 12)
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#define __swp_entry(type, offset) \
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((swp_entry_t) { ((type) << 5) | ((offset) << 12) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
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#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
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#define kern_addr_valid(addr) (1)
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#include <asm-generic/pgtable.h>
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/*
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* No page table caches to initialise
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*/
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#define pgtable_cache_init() do { } while (0)
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typedef pte_t *pte_addr_t;
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_OPENRISC_PGTABLE_H */
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