315 lines
6.8 KiB
C
315 lines
6.8 KiB
C
/*
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* Atheros AR71XX/AR724X/AR913X specific setup
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*
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* Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/of_fdt.h>
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#include <asm/bootinfo.h>
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#include <asm/idle.h>
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#include <asm/time.h> /* for mips_hpt_frequency */
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#include <asm/reboot.h> /* for _machine_{restart,halt} */
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#include <asm/mips_machine.h>
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#include <asm/prom.h>
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#include <asm/fw/fw.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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#include "dev-common.h"
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#include "machtypes.h"
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#define ATH79_SYS_TYPE_LEN 64
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static char ath79_sys_type[ATH79_SYS_TYPE_LEN];
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static void ath79_restart(char *command)
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{
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ath79_device_reset_set(AR71XX_RESET_FULL_CHIP);
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for (;;)
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if (cpu_wait)
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cpu_wait();
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}
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static void ath79_halt(void)
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{
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while (1)
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cpu_wait();
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}
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static void __init ath79_detect_sys_type(void)
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{
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char *chip = "????";
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u32 id;
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u32 major;
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u32 minor;
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u32 rev = 0;
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id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
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major = id & REV_ID_MAJOR_MASK;
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switch (major) {
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case REV_ID_MAJOR_AR71XX:
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minor = id & AR71XX_REV_ID_MINOR_MASK;
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rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
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rev &= AR71XX_REV_ID_REVISION_MASK;
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switch (minor) {
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case AR71XX_REV_ID_MINOR_AR7130:
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ath79_soc = ATH79_SOC_AR7130;
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chip = "7130";
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break;
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case AR71XX_REV_ID_MINOR_AR7141:
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ath79_soc = ATH79_SOC_AR7141;
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chip = "7141";
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break;
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case AR71XX_REV_ID_MINOR_AR7161:
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ath79_soc = ATH79_SOC_AR7161;
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chip = "7161";
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break;
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}
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break;
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case REV_ID_MAJOR_AR7240:
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ath79_soc = ATH79_SOC_AR7240;
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chip = "7240";
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rev = id & AR724X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR7241:
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ath79_soc = ATH79_SOC_AR7241;
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chip = "7241";
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rev = id & AR724X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR7242:
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ath79_soc = ATH79_SOC_AR7242;
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chip = "7242";
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rev = id & AR724X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR913X:
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minor = id & AR913X_REV_ID_MINOR_MASK;
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rev = id >> AR913X_REV_ID_REVISION_SHIFT;
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rev &= AR913X_REV_ID_REVISION_MASK;
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switch (minor) {
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case AR913X_REV_ID_MINOR_AR9130:
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ath79_soc = ATH79_SOC_AR9130;
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chip = "9130";
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break;
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case AR913X_REV_ID_MINOR_AR9132:
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ath79_soc = ATH79_SOC_AR9132;
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chip = "9132";
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break;
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}
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break;
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case REV_ID_MAJOR_AR9330:
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ath79_soc = ATH79_SOC_AR9330;
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chip = "9330";
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rev = id & AR933X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR9331:
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ath79_soc = ATH79_SOC_AR9331;
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chip = "9331";
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rev = id & AR933X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR9341:
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ath79_soc = ATH79_SOC_AR9341;
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chip = "9341";
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rev = id & AR934X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR9342:
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ath79_soc = ATH79_SOC_AR9342;
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chip = "9342";
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rev = id & AR934X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_AR9344:
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ath79_soc = ATH79_SOC_AR9344;
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chip = "9344";
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rev = id & AR934X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_QCA9556:
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ath79_soc = ATH79_SOC_QCA9556;
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chip = "9556";
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rev = id & QCA955X_REV_ID_REVISION_MASK;
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break;
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case REV_ID_MAJOR_QCA9558:
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ath79_soc = ATH79_SOC_QCA9558;
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chip = "9558";
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rev = id & QCA955X_REV_ID_REVISION_MASK;
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break;
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default:
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panic("ath79: unknown SoC, id:0x%08x", id);
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}
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ath79_soc_rev = rev;
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if (soc_is_qca955x())
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sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
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chip, rev);
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else
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sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
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pr_info("SoC: %s\n", ath79_sys_type);
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}
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const char *get_system_type(void)
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{
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return ath79_sys_type;
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}
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int get_c0_perfcount_int(void)
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{
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return ATH79_MISC_IRQ(5);
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}
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EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
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unsigned int get_c0_compare_int(void)
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{
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return CP0_LEGACY_COMPARE_IRQ;
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}
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void __init plat_mem_setup(void)
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{
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unsigned long fdt_start;
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set_io_port_base(KSEG1);
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/* Get the position of the FDT passed by the bootloader */
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fdt_start = fw_getenvl("fdt_start");
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if (fdt_start)
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__dt_setup_arch((void *)KSEG0ADDR(fdt_start));
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else if (fw_passed_dtb)
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__dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));
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if (mips_machtype != ATH79_MACH_GENERIC_OF) {
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ath79_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
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AR71XX_RESET_SIZE);
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ath79_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
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AR71XX_PLL_SIZE);
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ath79_detect_sys_type();
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ath79_ddr_ctrl_init();
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detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);
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/* OF machines should use the reset driver */
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_machine_restart = ath79_restart;
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}
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_machine_halt = ath79_halt;
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pm_power_off = ath79_halt;
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}
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static void __init ath79_of_plat_time_init(void)
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{
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struct device_node *np;
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struct clk *clk;
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unsigned long cpu_clk_rate;
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of_clk_init(NULL);
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np = of_get_cpu_node(0, NULL);
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if (!np) {
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pr_err("Failed to get CPU node\n");
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return;
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}
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk)) {
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pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
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return;
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}
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cpu_clk_rate = clk_get_rate(clk);
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pr_info("CPU clock: %lu.%03lu MHz\n",
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cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000);
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mips_hpt_frequency = cpu_clk_rate / 2;
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clk_put(clk);
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}
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void __init plat_time_init(void)
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{
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unsigned long cpu_clk_rate;
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unsigned long ahb_clk_rate;
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unsigned long ddr_clk_rate;
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unsigned long ref_clk_rate;
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if (IS_ENABLED(CONFIG_OF) && mips_machtype == ATH79_MACH_GENERIC_OF) {
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ath79_of_plat_time_init();
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return;
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}
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ath79_clocks_init();
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cpu_clk_rate = ath79_get_sys_clk_rate("cpu");
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ahb_clk_rate = ath79_get_sys_clk_rate("ahb");
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ddr_clk_rate = ath79_get_sys_clk_rate("ddr");
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ref_clk_rate = ath79_get_sys_clk_rate("ref");
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pr_info("Clocks: CPU:%lu.%03luMHz, DDR:%lu.%03luMHz, AHB:%lu.%03luMHz, Ref:%lu.%03luMHz\n",
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cpu_clk_rate / 1000000, (cpu_clk_rate / 1000) % 1000,
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ddr_clk_rate / 1000000, (ddr_clk_rate / 1000) % 1000,
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ahb_clk_rate / 1000000, (ahb_clk_rate / 1000) % 1000,
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ref_clk_rate / 1000000, (ref_clk_rate / 1000) % 1000);
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mips_hpt_frequency = cpu_clk_rate / 2;
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}
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static int __init ath79_setup(void)
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{
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if (mips_machtype == ATH79_MACH_GENERIC_OF)
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return 0;
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ath79_gpio_init();
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ath79_register_uart();
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ath79_register_wdt();
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mips_machine_setup();
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return 0;
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}
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arch_initcall(ath79_setup);
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void __init device_tree_init(void)
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{
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unflatten_and_copy_device_tree();
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}
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MIPS_MACHINE(ATH79_MACH_GENERIC,
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"Generic",
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"Generic AR71XX/AR724X/AR913X based board",
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NULL);
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MIPS_MACHINE(ATH79_MACH_GENERIC_OF,
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"DTB",
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"Generic AR71XX/AR724X/AR913X based board (DT)",
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NULL);
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