448 lines
12 KiB
C
448 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders
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*
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* Copyright (C) 2007 David Brownell
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*/
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#include <linux/gpio/driver.h>
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#include <linux/i2c.h>
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#include <linux/platform_data/pcf857x.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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static const struct i2c_device_id pcf857x_id[] = {
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{ "pcf8574", 8 },
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{ "pcf8574a", 8 },
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{ "pca8574", 8 },
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{ "pca9670", 8 },
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{ "pca9672", 8 },
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{ "pca9674", 8 },
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{ "pcf8575", 16 },
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{ "pca8575", 16 },
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{ "pca9671", 16 },
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{ "pca9673", 16 },
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{ "pca9675", 16 },
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{ "max7328", 8 },
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{ "max7329", 8 },
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, pcf857x_id);
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#ifdef CONFIG_OF
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static const struct of_device_id pcf857x_of_table[] = {
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{ .compatible = "nxp,pcf8574" },
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{ .compatible = "nxp,pcf8574a" },
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{ .compatible = "nxp,pca8574" },
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{ .compatible = "nxp,pca9670" },
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{ .compatible = "nxp,pca9672" },
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{ .compatible = "nxp,pca9674" },
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{ .compatible = "nxp,pcf8575" },
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{ .compatible = "nxp,pca8575" },
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{ .compatible = "nxp,pca9671" },
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{ .compatible = "nxp,pca9673" },
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{ .compatible = "nxp,pca9675" },
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{ .compatible = "maxim,max7328" },
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{ .compatible = "maxim,max7329" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, pcf857x_of_table);
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#endif
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/*
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* The pcf857x, pca857x, and pca967x chips only expose one read and one
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* write register. Writing a "one" bit (to match the reset state) lets
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* that pin be used as an input; it's not an open-drain model, but acts
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* a bit like one. This is described as "quasi-bidirectional"; read the
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* chip documentation for details.
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*
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* Many other I2C GPIO expander chips (like the pca953x models) have
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* more complex register models and more conventional circuitry using
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* push/pull drivers. They often use the same 0x20..0x27 addresses as
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* pcf857x parts, making the "legacy" I2C driver model problematic.
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*/
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struct pcf857x {
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struct gpio_chip chip;
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struct i2c_client *client;
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struct mutex lock; /* protect 'out' */
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unsigned out; /* software latch */
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unsigned status; /* current status */
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unsigned irq_enabled; /* enabled irqs */
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int (*write)(struct i2c_client *client, unsigned data);
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int (*read)(struct i2c_client *client);
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};
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/*-------------------------------------------------------------------------*/
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/* Talk to 8-bit I/O expander */
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static int i2c_write_le8(struct i2c_client *client, unsigned data)
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{
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return i2c_smbus_write_byte(client, data);
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}
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static int i2c_read_le8(struct i2c_client *client)
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{
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return (int)i2c_smbus_read_byte(client);
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}
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/* Talk to 16-bit I/O expander */
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static int i2c_write_le16(struct i2c_client *client, unsigned word)
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{
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u8 buf[2] = { word & 0xff, word >> 8, };
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int status;
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status = i2c_master_send(client, buf, 2);
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return (status < 0) ? status : 0;
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}
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static int i2c_read_le16(struct i2c_client *client)
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{
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u8 buf[2];
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int status;
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status = i2c_master_recv(client, buf, 2);
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if (status < 0)
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return status;
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return (buf[1] << 8) | buf[0];
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}
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/*-------------------------------------------------------------------------*/
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static int pcf857x_input(struct gpio_chip *chip, unsigned offset)
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{
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struct pcf857x *gpio = gpiochip_get_data(chip);
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int status;
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mutex_lock(&gpio->lock);
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gpio->out |= (1 << offset);
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status = gpio->write(gpio->client, gpio->out);
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mutex_unlock(&gpio->lock);
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return status;
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}
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static int pcf857x_get(struct gpio_chip *chip, unsigned offset)
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{
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struct pcf857x *gpio = gpiochip_get_data(chip);
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int value;
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value = gpio->read(gpio->client);
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return (value < 0) ? value : !!(value & (1 << offset));
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}
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static int pcf857x_output(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct pcf857x *gpio = gpiochip_get_data(chip);
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unsigned bit = 1 << offset;
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int status;
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mutex_lock(&gpio->lock);
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if (value)
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gpio->out |= bit;
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else
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gpio->out &= ~bit;
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status = gpio->write(gpio->client, gpio->out);
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mutex_unlock(&gpio->lock);
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return status;
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}
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static void pcf857x_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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pcf857x_output(chip, offset, value);
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}
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/*-------------------------------------------------------------------------*/
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static irqreturn_t pcf857x_irq(int irq, void *data)
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{
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struct pcf857x *gpio = data;
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unsigned long change, i, status;
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status = gpio->read(gpio->client);
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/*
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* call the interrupt handler iff gpio is used as
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* interrupt source, just to avoid bad irqs
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*/
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mutex_lock(&gpio->lock);
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change = (gpio->status ^ status) & gpio->irq_enabled;
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gpio->status = status;
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mutex_unlock(&gpio->lock);
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for_each_set_bit(i, &change, gpio->chip.ngpio)
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handle_nested_irq(irq_find_mapping(gpio->chip.irq.domain, i));
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return IRQ_HANDLED;
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}
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/*
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* NOP functions
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*/
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static void noop(struct irq_data *data) { }
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static int pcf857x_irq_set_wake(struct irq_data *data, unsigned int on)
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{
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struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
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return irq_set_irq_wake(gpio->client->irq, on);
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}
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static void pcf857x_irq_enable(struct irq_data *data)
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{
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struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
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irq_hw_number_t hwirq = irqd_to_hwirq(data);
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gpiochip_enable_irq(&gpio->chip, hwirq);
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gpio->irq_enabled |= (1 << hwirq);
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}
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static void pcf857x_irq_disable(struct irq_data *data)
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{
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struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
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irq_hw_number_t hwirq = irqd_to_hwirq(data);
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gpio->irq_enabled &= ~(1 << hwirq);
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gpiochip_disable_irq(&gpio->chip, hwirq);
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}
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static void pcf857x_irq_bus_lock(struct irq_data *data)
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{
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struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
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mutex_lock(&gpio->lock);
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}
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static void pcf857x_irq_bus_sync_unlock(struct irq_data *data)
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{
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struct pcf857x *gpio = irq_data_get_irq_chip_data(data);
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mutex_unlock(&gpio->lock);
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}
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static const struct irq_chip pcf857x_irq_chip = {
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.name = "pcf857x",
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.irq_enable = pcf857x_irq_enable,
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.irq_disable = pcf857x_irq_disable,
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.irq_ack = noop,
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.irq_mask = noop,
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.irq_unmask = noop,
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.irq_set_wake = pcf857x_irq_set_wake,
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.irq_bus_lock = pcf857x_irq_bus_lock,
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.irq_bus_sync_unlock = pcf857x_irq_bus_sync_unlock,
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.flags = IRQCHIP_IMMUTABLE,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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/*-------------------------------------------------------------------------*/
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static int pcf857x_probe(struct i2c_client *client)
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{
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const struct i2c_device_id *id = i2c_client_get_device_id(client);
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struct pcf857x_platform_data *pdata = dev_get_platdata(&client->dev);
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struct device_node *np = client->dev.of_node;
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struct pcf857x *gpio;
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unsigned int n_latch = 0;
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int status;
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if (IS_ENABLED(CONFIG_OF) && np)
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of_property_read_u32(np, "lines-initial-states", &n_latch);
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else if (pdata)
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n_latch = pdata->n_latch;
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else
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dev_dbg(&client->dev, "no platform data\n");
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/* Allocate, initialize, and register this gpio_chip. */
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gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL);
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if (!gpio)
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return -ENOMEM;
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mutex_init(&gpio->lock);
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gpio->chip.base = pdata ? pdata->gpio_base : -1;
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gpio->chip.can_sleep = true;
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gpio->chip.parent = &client->dev;
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gpio->chip.owner = THIS_MODULE;
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gpio->chip.get = pcf857x_get;
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gpio->chip.set = pcf857x_set;
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gpio->chip.direction_input = pcf857x_input;
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gpio->chip.direction_output = pcf857x_output;
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gpio->chip.ngpio = id->driver_data;
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/* NOTE: the OnSemi jlc1562b is also largely compatible with
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* these parts, notably for output. It has a low-resolution
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* DAC instead of pin change IRQs; and its inputs can be the
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* result of comparators.
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*/
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/* 8574 addresses are 0x20..0x27; 8574a uses 0x38..0x3f;
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* 9670, 9672, 9764, and 9764a use quite a variety.
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*
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* NOTE: we don't distinguish here between *4 and *4a parts.
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*/
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if (gpio->chip.ngpio == 8) {
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gpio->write = i2c_write_le8;
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gpio->read = i2c_read_le8;
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if (!i2c_check_functionality(client->adapter,
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I2C_FUNC_SMBUS_BYTE))
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status = -EIO;
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/* fail if there's no chip present */
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else
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status = i2c_smbus_read_byte(client);
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/* '75/'75c addresses are 0x20..0x27, just like the '74;
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* the '75c doesn't have a current source pulling high.
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* 9671, 9673, and 9765 use quite a variety of addresses.
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*
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* NOTE: we don't distinguish here between '75 and '75c parts.
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*/
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} else if (gpio->chip.ngpio == 16) {
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gpio->write = i2c_write_le16;
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gpio->read = i2c_read_le16;
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if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
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status = -EIO;
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/* fail if there's no chip present */
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else
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status = i2c_read_le16(client);
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} else {
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dev_dbg(&client->dev, "unsupported number of gpios\n");
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status = -EINVAL;
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}
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if (status < 0)
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goto fail;
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gpio->chip.label = client->name;
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gpio->client = client;
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i2c_set_clientdata(client, gpio);
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/* NOTE: these chips have strange "quasi-bidirectional" I/O pins.
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* We can't actually know whether a pin is configured (a) as output
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* and driving the signal low, or (b) as input and reporting a low
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* value ... without knowing the last value written since the chip
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* came out of reset (if any). We can't read the latched output.
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*
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* In short, the only reliable solution for setting up pin direction
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* is to do it explicitly. The setup() method can do that, but it
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* may cause transient glitching since it can't know the last value
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* written (some pins may need to be driven low).
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*
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* Using n_latch avoids that trouble. When left initialized to zero,
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* our software copy of the "latch" then matches the chip's all-ones
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* reset state. Otherwise it flags pins to be driven low.
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*/
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gpio->out = ~n_latch;
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gpio->status = gpio->read(gpio->client);
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/* Enable irqchip if we have an interrupt */
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if (client->irq) {
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struct gpio_irq_chip *girq;
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status = devm_request_threaded_irq(&client->dev, client->irq,
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NULL, pcf857x_irq, IRQF_ONESHOT |
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IRQF_TRIGGER_FALLING | IRQF_SHARED,
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dev_name(&client->dev), gpio);
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if (status)
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goto fail;
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girq = &gpio->chip.irq;
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gpio_irq_chip_set_chip(girq, &pcf857x_irq_chip);
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/* This will let us handle the parent IRQ in the driver */
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girq->parent_handler = NULL;
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girq->num_parents = 0;
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girq->parents = NULL;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_level_irq;
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girq->threaded = true;
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}
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status = devm_gpiochip_add_data(&client->dev, &gpio->chip, gpio);
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if (status < 0)
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goto fail;
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/* Let platform code set up the GPIOs and their users.
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* Now is the first time anyone could use them.
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*/
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if (pdata && pdata->setup) {
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status = pdata->setup(client,
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gpio->chip.base, gpio->chip.ngpio,
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pdata->context);
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if (status < 0)
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dev_warn(&client->dev, "setup --> %d\n", status);
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}
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dev_info(&client->dev, "probed\n");
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return 0;
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fail:
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dev_dbg(&client->dev, "probe error %d for '%s'\n", status,
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client->name);
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return status;
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}
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static void pcf857x_remove(struct i2c_client *client)
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{
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struct pcf857x_platform_data *pdata = dev_get_platdata(&client->dev);
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struct pcf857x *gpio = i2c_get_clientdata(client);
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if (pdata && pdata->teardown)
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pdata->teardown(client, gpio->chip.base, gpio->chip.ngpio,
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pdata->context);
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}
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static void pcf857x_shutdown(struct i2c_client *client)
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{
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struct pcf857x *gpio = i2c_get_clientdata(client);
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/* Drive all the I/O lines high */
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gpio->write(gpio->client, BIT(gpio->chip.ngpio) - 1);
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}
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static struct i2c_driver pcf857x_driver = {
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.driver = {
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.name = "pcf857x",
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.of_match_table = of_match_ptr(pcf857x_of_table),
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},
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.probe_new = pcf857x_probe,
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.remove = pcf857x_remove,
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.shutdown = pcf857x_shutdown,
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.id_table = pcf857x_id,
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};
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static int __init pcf857x_init(void)
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{
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return i2c_add_driver(&pcf857x_driver);
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}
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/* register after i2c postcore initcall and before
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* subsys initcalls that may rely on these GPIOs
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*/
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subsys_initcall(pcf857x_init);
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static void __exit pcf857x_exit(void)
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{
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i2c_del_driver(&pcf857x_driver);
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}
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module_exit(pcf857x_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("David Brownell");
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