261 lines
6.2 KiB
C
261 lines
6.2 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2011, 2012 Cavium, Inc.
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*/
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/spi/spi.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-mpi-defs.h>
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#define OCTEON_SPI_CFG 0
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#define OCTEON_SPI_STS 0x08
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#define OCTEON_SPI_TX 0x10
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#define OCTEON_SPI_DAT0 0x80
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#define OCTEON_SPI_MAX_BYTES 9
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#define OCTEON_SPI_MAX_CLOCK_HZ 16000000
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struct octeon_spi {
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u64 register_base;
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u64 last_cfg;
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u64 cs_enax;
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};
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static void octeon_spi_wait_ready(struct octeon_spi *p)
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{
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union cvmx_mpi_sts mpi_sts;
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unsigned int loops = 0;
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do {
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if (loops++)
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__delay(500);
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mpi_sts.u64 = cvmx_read_csr(p->register_base + OCTEON_SPI_STS);
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} while (mpi_sts.s.busy);
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}
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static int octeon_spi_do_transfer(struct octeon_spi *p,
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struct spi_message *msg,
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struct spi_transfer *xfer,
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bool last_xfer)
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{
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struct spi_device *spi = msg->spi;
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union cvmx_mpi_cfg mpi_cfg;
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union cvmx_mpi_tx mpi_tx;
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unsigned int clkdiv;
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unsigned int speed_hz;
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int mode;
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bool cpha, cpol;
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const u8 *tx_buf;
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u8 *rx_buf;
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int len;
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int i;
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mode = spi->mode;
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cpha = mode & SPI_CPHA;
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cpol = mode & SPI_CPOL;
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speed_hz = xfer->speed_hz ? : spi->max_speed_hz;
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clkdiv = octeon_get_io_clock_rate() / (2 * speed_hz);
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mpi_cfg.u64 = 0;
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mpi_cfg.s.clkdiv = clkdiv;
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mpi_cfg.s.cshi = (mode & SPI_CS_HIGH) ? 1 : 0;
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mpi_cfg.s.lsbfirst = (mode & SPI_LSB_FIRST) ? 1 : 0;
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mpi_cfg.s.wireor = (mode & SPI_3WIRE) ? 1 : 0;
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mpi_cfg.s.idlelo = cpha != cpol;
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mpi_cfg.s.cslate = cpha ? 1 : 0;
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mpi_cfg.s.enable = 1;
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if (spi->chip_select < 4)
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p->cs_enax |= 1ull << (12 + spi->chip_select);
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mpi_cfg.u64 |= p->cs_enax;
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if (mpi_cfg.u64 != p->last_cfg) {
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p->last_cfg = mpi_cfg.u64;
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cvmx_write_csr(p->register_base + OCTEON_SPI_CFG, mpi_cfg.u64);
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}
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tx_buf = xfer->tx_buf;
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rx_buf = xfer->rx_buf;
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len = xfer->len;
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while (len > OCTEON_SPI_MAX_BYTES) {
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for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
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u8 d;
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if (tx_buf)
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d = *tx_buf++;
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else
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d = 0;
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cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d);
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}
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mpi_tx.u64 = 0;
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mpi_tx.s.csid = spi->chip_select;
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mpi_tx.s.leavecs = 1;
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mpi_tx.s.txnum = tx_buf ? OCTEON_SPI_MAX_BYTES : 0;
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mpi_tx.s.totnum = OCTEON_SPI_MAX_BYTES;
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cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64);
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octeon_spi_wait_ready(p);
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if (rx_buf)
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for (i = 0; i < OCTEON_SPI_MAX_BYTES; i++) {
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u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
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*rx_buf++ = (u8)v;
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}
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len -= OCTEON_SPI_MAX_BYTES;
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}
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for (i = 0; i < len; i++) {
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u8 d;
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if (tx_buf)
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d = *tx_buf++;
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else
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d = 0;
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cvmx_write_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i), d);
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}
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mpi_tx.u64 = 0;
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mpi_tx.s.csid = spi->chip_select;
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if (last_xfer)
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mpi_tx.s.leavecs = xfer->cs_change;
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else
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mpi_tx.s.leavecs = !xfer->cs_change;
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mpi_tx.s.txnum = tx_buf ? len : 0;
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mpi_tx.s.totnum = len;
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cvmx_write_csr(p->register_base + OCTEON_SPI_TX, mpi_tx.u64);
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octeon_spi_wait_ready(p);
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if (rx_buf)
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for (i = 0; i < len; i++) {
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u64 v = cvmx_read_csr(p->register_base + OCTEON_SPI_DAT0 + (8 * i));
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*rx_buf++ = (u8)v;
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}
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if (xfer->delay_usecs)
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udelay(xfer->delay_usecs);
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return xfer->len;
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}
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static int octeon_spi_transfer_one_message(struct spi_master *master,
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struct spi_message *msg)
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{
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struct octeon_spi *p = spi_master_get_devdata(master);
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unsigned int total_len = 0;
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int status = 0;
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struct spi_transfer *xfer;
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list_for_each_entry(xfer, &msg->transfers, transfer_list) {
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bool last_xfer = list_is_last(&xfer->transfer_list,
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&msg->transfers);
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int r = octeon_spi_do_transfer(p, msg, xfer, last_xfer);
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if (r < 0) {
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status = r;
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goto err;
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}
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total_len += r;
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}
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err:
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msg->status = status;
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msg->actual_length = total_len;
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spi_finalize_current_message(master);
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return status;
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}
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static int octeon_spi_probe(struct platform_device *pdev)
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{
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struct resource *res_mem;
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struct spi_master *master;
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struct octeon_spi *p;
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int err = -ENOENT;
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master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
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if (!master)
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return -ENOMEM;
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p = spi_master_get_devdata(master);
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platform_set_drvdata(pdev, master);
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res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (res_mem == NULL) {
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dev_err(&pdev->dev, "found no memory resource\n");
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err = -ENXIO;
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goto fail;
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}
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if (!devm_request_mem_region(&pdev->dev, res_mem->start,
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resource_size(res_mem), res_mem->name)) {
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dev_err(&pdev->dev, "request_mem_region failed\n");
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goto fail;
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}
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p->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start,
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resource_size(res_mem));
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master->num_chipselect = 4;
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master->mode_bits = SPI_CPHA |
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SPI_CPOL |
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SPI_CS_HIGH |
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SPI_LSB_FIRST |
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SPI_3WIRE;
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master->transfer_one_message = octeon_spi_transfer_one_message;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
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master->dev.of_node = pdev->dev.of_node;
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err = devm_spi_register_master(&pdev->dev, master);
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if (err) {
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dev_err(&pdev->dev, "register master failed: %d\n", err);
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goto fail;
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}
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dev_info(&pdev->dev, "OCTEON SPI bus driver\n");
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return 0;
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fail:
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spi_master_put(master);
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return err;
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}
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static int octeon_spi_remove(struct platform_device *pdev)
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{
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struct spi_master *master = platform_get_drvdata(pdev);
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struct octeon_spi *p = spi_master_get_devdata(master);
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u64 register_base = p->register_base;
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/* Clear the CSENA* and put everything in a known state. */
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cvmx_write_csr(register_base + OCTEON_SPI_CFG, 0);
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return 0;
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}
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static struct of_device_id octeon_spi_match[] = {
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{ .compatible = "cavium,octeon-3010-spi", },
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{},
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};
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MODULE_DEVICE_TABLE(of, octeon_spi_match);
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static struct platform_driver octeon_spi_driver = {
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.driver = {
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.name = "spi-octeon",
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.of_match_table = octeon_spi_match,
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},
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.probe = octeon_spi_probe,
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.remove = octeon_spi_remove,
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};
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module_platform_driver(octeon_spi_driver);
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MODULE_DESCRIPTION("Cavium, Inc. OCTEON SPI bus driver");
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MODULE_AUTHOR("David Daney");
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MODULE_LICENSE("GPL");
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