95 lines
3.7 KiB
C
95 lines
3.7 KiB
C
/*
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* Copyright (C) 2007 ARM Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __ASM_ARCH_BOARD_EB_H
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#define __ASM_ARCH_BOARD_EB_H
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#include "platform.h"
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/*
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* RealView EB + ARM11MPCore peripheral addresses
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*/
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#define REALVIEW_EB_UART0_BASE 0x10009000 /* UART 0 */
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#define REALVIEW_EB_UART1_BASE 0x1000A000 /* UART 1 */
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#define REALVIEW_EB_UART2_BASE 0x1000B000 /* UART 2 */
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#define REALVIEW_EB_UART3_BASE 0x1000C000 /* UART 3 */
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#define REALVIEW_EB_SSP_BASE 0x1000D000 /* Synchronous Serial Port */
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#define REALVIEW_EB_WATCHDOG_BASE 0x10010000 /* watchdog interface */
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#define REALVIEW_EB_TIMER0_1_BASE 0x10011000 /* Timer 0 and 1 */
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#define REALVIEW_EB_TIMER2_3_BASE 0x10012000 /* Timer 2 and 3 */
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#define REALVIEW_EB_GPIO0_BASE 0x10013000 /* GPIO port 0 */
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#define REALVIEW_EB_RTC_BASE 0x10017000 /* Real Time Clock */
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#define REALVIEW_EB_CLCD_BASE 0x10020000 /* CLCD */
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#define REALVIEW_EB_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
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#define REALVIEW_EB_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
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#define REALVIEW_EB_SMC_BASE 0x10080000 /* Static memory controller */
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#define REALVIEW_EB_FLASH_BASE 0x40000000
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#define REALVIEW_EB_FLASH_SIZE SZ_64M
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#define REALVIEW_EB_ETH_BASE 0x4E000000 /* Ethernet */
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#define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */
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#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
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#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x10100000
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#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */
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#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
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#else
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#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000
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#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */
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#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
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#endif
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#define REALVIEW_EB11MP_PRIV_MEM_SIZE SZ_8K
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#define REALVIEW_EB11MP_PRIV_MEM_OFF(x) (REALVIEW_EB11MP_PRIV_MEM_BASE + (x))
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#define REALVIEW_EB11MP_SCU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0) /* SCU registers */
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#define REALVIEW_EB11MP_GIC_CPU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0100) /* Generic interrupt controller CPU interface */
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#define REALVIEW_EB11MP_TWD_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0600)
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#define REALVIEW_EB11MP_GIC_DIST_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x1000) /* Generic interrupt controller distributor */
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/*
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* Core tile identification (REALVIEW_SYS_PROCID)
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*/
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#define REALVIEW_EB_PROC_MASK 0xFF000000
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#define REALVIEW_EB_PROC_ARM7TDMI 0x00000000
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#define REALVIEW_EB_PROC_ARM9 0x02000000
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#define REALVIEW_EB_PROC_ARM11 0x04000000
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#define REALVIEW_EB_PROC_ARM11MP 0x06000000
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#define REALVIEW_EB_PROC_A9MP 0x0C000000
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#define check_eb_proc(proc_type) \
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((readl(__io_address(REALVIEW_SYS_PROCID)) & REALVIEW_EB_PROC_MASK) \
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== proc_type)
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#ifdef CONFIG_REALVIEW_EB_ARM11MP
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#define core_tile_eb11mp() check_eb_proc(REALVIEW_EB_PROC_ARM11MP)
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#else
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#define core_tile_eb11mp() 0
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#endif
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#ifdef CONFIG_REALVIEW_EB_A9MP
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#define core_tile_a9mp() check_eb_proc(REALVIEW_EB_PROC_A9MP)
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#else
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#define core_tile_a9mp() 0
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#endif
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#define machine_is_realview_eb_mp() \
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(machine_is_realview_eb() && (core_tile_eb11mp() || core_tile_a9mp()))
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#endif /* __ASM_ARCH_BOARD_EB_H */
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