317 lines
7.7 KiB
C
317 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (C) 2016 Broadcom
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#include <linux/acpi.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/nvmem-provider.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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/*
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* # of tries for OTP Status. The time to execute a command varies. The slowest
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* commands are writes which also vary based on the # of bits turned on. Writing
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* 0xffffffff takes ~3800 us.
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*/
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#define OTPC_RETRIES 5000
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/* Sequence to enable OTP program */
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#define OTPC_PROG_EN_SEQ { 0xf, 0x4, 0x8, 0xd }
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/* OTPC Commands */
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#define OTPC_CMD_READ 0x0
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#define OTPC_CMD_OTP_PROG_ENABLE 0x2
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#define OTPC_CMD_OTP_PROG_DISABLE 0x3
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#define OTPC_CMD_PROGRAM 0x8
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/* OTPC Status Bits */
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#define OTPC_STAT_CMD_DONE BIT(1)
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#define OTPC_STAT_PROG_OK BIT(2)
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/* OTPC register definition */
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#define OTPC_MODE_REG_OFFSET 0x0
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#define OTPC_MODE_REG_OTPC_MODE 0
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#define OTPC_COMMAND_OFFSET 0x4
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#define OTPC_COMMAND_COMMAND_WIDTH 6
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#define OTPC_CMD_START_OFFSET 0x8
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#define OTPC_CMD_START_START 0
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#define OTPC_CPU_STATUS_OFFSET 0xc
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#define OTPC_CPUADDR_REG_OFFSET 0x28
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#define OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH 16
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#define OTPC_CPU_WRITE_REG_OFFSET 0x2c
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#define OTPC_CMD_MASK (BIT(OTPC_COMMAND_COMMAND_WIDTH) - 1)
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#define OTPC_ADDR_MASK (BIT(OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH) - 1)
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struct otpc_map {
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/* in words. */
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u32 otpc_row_size;
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/* 128 bit row / 4 words support. */
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u16 data_r_offset[4];
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/* 128 bit row / 4 words support. */
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u16 data_w_offset[4];
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};
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static struct otpc_map otp_map = {
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.otpc_row_size = 1,
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.data_r_offset = {0x10},
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.data_w_offset = {0x2c},
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};
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static struct otpc_map otp_map_v2 = {
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.otpc_row_size = 2,
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.data_r_offset = {0x10, 0x5c},
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.data_w_offset = {0x2c, 0x64},
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};
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struct otpc_priv {
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struct device *dev;
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void __iomem *base;
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const struct otpc_map *map;
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struct nvmem_config *config;
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};
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static inline void set_command(void __iomem *base, u32 command)
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{
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writel(command & OTPC_CMD_MASK, base + OTPC_COMMAND_OFFSET);
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}
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static inline void set_cpu_address(void __iomem *base, u32 addr)
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{
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writel(addr & OTPC_ADDR_MASK, base + OTPC_CPUADDR_REG_OFFSET);
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}
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static inline void set_start_bit(void __iomem *base)
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{
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writel(1 << OTPC_CMD_START_START, base + OTPC_CMD_START_OFFSET);
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}
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static inline void reset_start_bit(void __iomem *base)
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{
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writel(0, base + OTPC_CMD_START_OFFSET);
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}
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static inline void write_cpu_data(void __iomem *base, u32 value)
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{
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writel(value, base + OTPC_CPU_WRITE_REG_OFFSET);
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}
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static int poll_cpu_status(void __iomem *base, u32 value)
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{
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u32 status;
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u32 retries;
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for (retries = 0; retries < OTPC_RETRIES; retries++) {
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status = readl(base + OTPC_CPU_STATUS_OFFSET);
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if (status & value)
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break;
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udelay(1);
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}
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if (retries == OTPC_RETRIES)
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return -EAGAIN;
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return 0;
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}
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static int enable_ocotp_program(void __iomem *base)
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{
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static const u32 vals[] = OTPC_PROG_EN_SEQ;
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int i;
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int ret;
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/* Write the magic sequence to enable programming */
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set_command(base, OTPC_CMD_OTP_PROG_ENABLE);
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for (i = 0; i < ARRAY_SIZE(vals); i++) {
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write_cpu_data(base, vals[i]);
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set_start_bit(base);
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ret = poll_cpu_status(base, OTPC_STAT_CMD_DONE);
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reset_start_bit(base);
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if (ret)
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return ret;
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}
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return poll_cpu_status(base, OTPC_STAT_PROG_OK);
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}
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static int disable_ocotp_program(void __iomem *base)
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{
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int ret;
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set_command(base, OTPC_CMD_OTP_PROG_DISABLE);
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set_start_bit(base);
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ret = poll_cpu_status(base, OTPC_STAT_PROG_OK);
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reset_start_bit(base);
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return ret;
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}
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static int bcm_otpc_read(void *context, unsigned int offset, void *val,
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size_t bytes)
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{
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struct otpc_priv *priv = context;
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u32 *buf = val;
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u32 bytes_read;
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u32 address = offset / priv->config->word_size;
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int i, ret;
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for (bytes_read = 0; bytes_read < bytes;) {
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set_command(priv->base, OTPC_CMD_READ);
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set_cpu_address(priv->base, address++);
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set_start_bit(priv->base);
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ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
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if (ret) {
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dev_err(priv->dev, "otp read error: 0x%x", ret);
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return -EIO;
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}
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for (i = 0; i < priv->map->otpc_row_size; i++) {
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*buf++ = readl(priv->base +
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priv->map->data_r_offset[i]);
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bytes_read += sizeof(*buf);
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}
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reset_start_bit(priv->base);
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}
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return 0;
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}
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static int bcm_otpc_write(void *context, unsigned int offset, void *val,
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size_t bytes)
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{
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struct otpc_priv *priv = context;
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u32 *buf = val;
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u32 bytes_written;
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u32 address = offset / priv->config->word_size;
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int i, ret;
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if (offset % priv->config->word_size)
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return -EINVAL;
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ret = enable_ocotp_program(priv->base);
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if (ret)
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return -EIO;
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for (bytes_written = 0; bytes_written < bytes;) {
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set_command(priv->base, OTPC_CMD_PROGRAM);
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set_cpu_address(priv->base, address++);
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for (i = 0; i < priv->map->otpc_row_size; i++) {
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writel(*buf, priv->base + priv->map->data_w_offset[i]);
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buf++;
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bytes_written += sizeof(*buf);
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}
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set_start_bit(priv->base);
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ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
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reset_start_bit(priv->base);
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if (ret) {
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dev_err(priv->dev, "otp write error: 0x%x", ret);
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return -EIO;
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}
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}
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disable_ocotp_program(priv->base);
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return 0;
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}
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static struct nvmem_config bcm_otpc_nvmem_config = {
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.name = "bcm-ocotp",
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.read_only = false,
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.word_size = 4,
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.stride = 4,
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.reg_read = bcm_otpc_read,
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.reg_write = bcm_otpc_write,
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};
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static const struct of_device_id bcm_otpc_dt_ids[] = {
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{ .compatible = "brcm,ocotp", .data = &otp_map },
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{ .compatible = "brcm,ocotp-v2", .data = &otp_map_v2 },
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{ },
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};
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MODULE_DEVICE_TABLE(of, bcm_otpc_dt_ids);
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static const struct acpi_device_id bcm_otpc_acpi_ids[] __maybe_unused = {
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{ .id = "BRCM0700", .driver_data = (kernel_ulong_t)&otp_map },
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{ .id = "BRCM0701", .driver_data = (kernel_ulong_t)&otp_map_v2 },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(acpi, bcm_otpc_acpi_ids);
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static int bcm_otpc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *res;
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struct otpc_priv *priv;
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struct nvmem_device *nvmem;
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int err;
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u32 num_words;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->map = device_get_match_data(dev);
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if (!priv->map)
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return -ENODEV;
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/* Get OTP base address register. */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(priv->base)) {
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dev_err(dev, "unable to map I/O memory\n");
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return PTR_ERR(priv->base);
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}
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/* Enable CPU access to OTPC. */
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writel(readl(priv->base + OTPC_MODE_REG_OFFSET) |
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BIT(OTPC_MODE_REG_OTPC_MODE),
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priv->base + OTPC_MODE_REG_OFFSET);
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reset_start_bit(priv->base);
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/* Read size of memory in words. */
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err = device_property_read_u32(dev, "brcm,ocotp-size", &num_words);
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if (err) {
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dev_err(dev, "size parameter not specified\n");
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return -EINVAL;
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} else if (num_words == 0) {
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dev_err(dev, "size must be > 0\n");
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return -EINVAL;
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}
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bcm_otpc_nvmem_config.size = 4 * num_words;
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bcm_otpc_nvmem_config.dev = dev;
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bcm_otpc_nvmem_config.priv = priv;
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if (priv->map == &otp_map_v2) {
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bcm_otpc_nvmem_config.word_size = 8;
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bcm_otpc_nvmem_config.stride = 8;
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}
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priv->config = &bcm_otpc_nvmem_config;
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nvmem = devm_nvmem_register(dev, &bcm_otpc_nvmem_config);
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if (IS_ERR(nvmem)) {
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dev_err(dev, "error registering nvmem config\n");
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return PTR_ERR(nvmem);
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}
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return 0;
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}
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static struct platform_driver bcm_otpc_driver = {
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.probe = bcm_otpc_probe,
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.driver = {
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.name = "brcm-otpc",
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.of_match_table = bcm_otpc_dt_ids,
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.acpi_match_table = ACPI_PTR(bcm_otpc_acpi_ids),
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},
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};
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module_platform_driver(bcm_otpc_driver);
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MODULE_DESCRIPTION("Broadcom OTPC driver");
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MODULE_LICENSE("GPL v2");
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