445 lines
15 KiB
C
445 lines
15 KiB
C
#ifndef _INTEL_RINGBUFFER_H_
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#define _INTEL_RINGBUFFER_H_
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#include <linux/hashtable.h>
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#define I915_CMD_HASH_ORDER 9
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/* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
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* but keeps the logic simple. Indeed, the whole purpose of this macro is just
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* to give some inclination as to some of the magic values used in the various
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* workarounds!
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*/
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#define CACHELINE_BYTES 64
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/*
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* Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use"
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* Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use"
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* Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use"
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*
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* "If the Ring Buffer Head Pointer and the Tail Pointer are on the same
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* cacheline, the Head Pointer must not be greater than the Tail
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* Pointer."
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*/
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#define I915_RING_FREE_SPACE 64
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struct intel_hw_status_page {
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u32 *page_addr;
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unsigned int gfx_addr;
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struct drm_i915_gem_object *obj;
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};
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#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
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#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
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#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
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#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
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#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
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#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
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#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
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#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
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#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
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#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
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#define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
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#define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val)
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/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
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* do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
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*/
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#define i915_semaphore_seqno_size sizeof(uint64_t)
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#define GEN8_SIGNAL_OFFSET(__ring, to) \
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(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
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((__ring)->id * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
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(i915_semaphore_seqno_size * (to)))
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#define GEN8_WAIT_OFFSET(__ring, from) \
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(i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \
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((from) * I915_NUM_RINGS * i915_semaphore_seqno_size) + \
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(i915_semaphore_seqno_size * (__ring)->id))
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#define GEN8_RING_SEMAPHORE_INIT do { \
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if (!dev_priv->semaphore_obj) { \
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break; \
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} \
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ring->semaphore.signal_ggtt[RCS] = GEN8_SIGNAL_OFFSET(ring, RCS); \
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ring->semaphore.signal_ggtt[VCS] = GEN8_SIGNAL_OFFSET(ring, VCS); \
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ring->semaphore.signal_ggtt[BCS] = GEN8_SIGNAL_OFFSET(ring, BCS); \
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ring->semaphore.signal_ggtt[VECS] = GEN8_SIGNAL_OFFSET(ring, VECS); \
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ring->semaphore.signal_ggtt[VCS2] = GEN8_SIGNAL_OFFSET(ring, VCS2); \
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ring->semaphore.signal_ggtt[ring->id] = MI_SEMAPHORE_SYNC_INVALID; \
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} while(0)
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enum intel_ring_hangcheck_action {
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HANGCHECK_IDLE = 0,
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HANGCHECK_WAIT,
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HANGCHECK_ACTIVE,
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HANGCHECK_ACTIVE_LOOP,
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HANGCHECK_KICK,
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HANGCHECK_HUNG,
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};
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#define HANGCHECK_SCORE_RING_HUNG 31
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struct intel_ring_hangcheck {
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u64 acthd;
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u64 max_acthd;
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u32 seqno;
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int score;
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enum intel_ring_hangcheck_action action;
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int deadlock;
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};
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struct intel_ringbuffer {
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struct drm_i915_gem_object *obj;
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void __iomem *virtual_start;
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struct intel_engine_cs *ring;
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u32 head;
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u32 tail;
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int space;
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int size;
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int effective_size;
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/** We track the position of the requests in the ring buffer, and
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* when each is retired we increment last_retired_head as the GPU
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* must have finished processing the request and so we know we
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* can advance the ringbuffer up to that position.
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*
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* last_retired_head is set to -1 after the value is consumed so
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* we can detect new retirements.
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*/
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u32 last_retired_head;
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};
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struct intel_context;
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struct intel_engine_cs {
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const char *name;
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enum intel_ring_id {
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RCS = 0x0,
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VCS,
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BCS,
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VECS,
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VCS2
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} id;
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#define I915_NUM_RINGS 5
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#define LAST_USER_RING (VECS + 1)
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u32 mmio_base;
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struct drm_device *dev;
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struct intel_ringbuffer *buffer;
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struct intel_hw_status_page status_page;
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unsigned irq_refcount; /* protected by dev_priv->irq_lock */
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u32 irq_enable_mask; /* bitmask to enable ring interrupt */
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struct drm_i915_gem_request *trace_irq_req;
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bool __must_check (*irq_get)(struct intel_engine_cs *ring);
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void (*irq_put)(struct intel_engine_cs *ring);
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int (*init_hw)(struct intel_engine_cs *ring);
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int (*init_context)(struct intel_engine_cs *ring,
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struct intel_context *ctx);
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void (*write_tail)(struct intel_engine_cs *ring,
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u32 value);
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int __must_check (*flush)(struct intel_engine_cs *ring,
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u32 invalidate_domains,
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u32 flush_domains);
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int (*add_request)(struct intel_engine_cs *ring);
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/* Some chipsets are not quite as coherent as advertised and need
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* an expensive kick to force a true read of the up-to-date seqno.
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* However, the up-to-date seqno is not always required and the last
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* seen value is good enough. Note that the seqno will always be
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* monotonic, even if not coherent.
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*/
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u32 (*get_seqno)(struct intel_engine_cs *ring,
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bool lazy_coherency);
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void (*set_seqno)(struct intel_engine_cs *ring,
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u32 seqno);
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int (*dispatch_execbuffer)(struct intel_engine_cs *ring,
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u64 offset, u32 length,
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unsigned flags);
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#define I915_DISPATCH_SECURE 0x1
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#define I915_DISPATCH_PINNED 0x2
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void (*cleanup)(struct intel_engine_cs *ring);
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/* GEN8 signal/wait table - never trust comments!
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* signal to signal to signal to signal to signal to
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* RCS VCS BCS VECS VCS2
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* --------------------------------------------------------------------
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* RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) |
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* |-------------------------------------------------------------------
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* VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) |
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* |-------------------------------------------------------------------
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* BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) |
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* |-------------------------------------------------------------------
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* VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) |
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* |-------------------------------------------------------------------
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* VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) |
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* |-------------------------------------------------------------------
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*
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* Generalization:
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* f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id)
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* ie. transpose of g(x, y)
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*
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* sync from sync from sync from sync from sync from
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* RCS VCS BCS VECS VCS2
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* --------------------------------------------------------------------
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* RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) |
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* |-------------------------------------------------------------------
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* VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) |
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* |-------------------------------------------------------------------
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* BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) |
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* |-------------------------------------------------------------------
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* VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) |
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* |-------------------------------------------------------------------
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* VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) |
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* |-------------------------------------------------------------------
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*
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* Generalization:
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* g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id)
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* ie. transpose of f(x, y)
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*/
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struct {
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u32 sync_seqno[I915_NUM_RINGS-1];
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union {
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struct {
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/* our mbox written by others */
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u32 wait[I915_NUM_RINGS];
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/* mboxes this ring signals to */
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u32 signal[I915_NUM_RINGS];
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} mbox;
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u64 signal_ggtt[I915_NUM_RINGS];
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};
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/* AKA wait() */
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int (*sync_to)(struct intel_engine_cs *ring,
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struct intel_engine_cs *to,
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u32 seqno);
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int (*signal)(struct intel_engine_cs *signaller,
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/* num_dwords needed by caller */
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unsigned int num_dwords);
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} semaphore;
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/* Execlists */
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spinlock_t execlist_lock;
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struct list_head execlist_queue;
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struct list_head execlist_retired_req_list;
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u8 next_context_status_buffer;
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u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
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int (*emit_request)(struct intel_ringbuffer *ringbuf,
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struct drm_i915_gem_request *request);
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int (*emit_flush)(struct intel_ringbuffer *ringbuf,
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struct intel_context *ctx,
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u32 invalidate_domains,
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u32 flush_domains);
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int (*emit_bb_start)(struct intel_ringbuffer *ringbuf,
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struct intel_context *ctx,
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u64 offset, unsigned flags);
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/**
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* List of objects currently involved in rendering from the
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* ringbuffer.
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*
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* Includes buffers having the contents of their GPU caches
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* flushed, not necessarily primitives. last_read_req
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* represents when the rendering involved will be completed.
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*
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* A reference is held on the buffer while on this list.
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*/
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struct list_head active_list;
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/**
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* List of breadcrumbs associated with GPU requests currently
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* outstanding.
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*/
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struct list_head request_list;
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/**
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* Do we have some not yet emitted requests outstanding?
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*/
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struct drm_i915_gem_request *outstanding_lazy_request;
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bool gpu_caches_dirty;
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bool fbc_dirty;
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wait_queue_head_t irq_queue;
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struct intel_context *default_context;
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struct intel_context *last_context;
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struct intel_ring_hangcheck hangcheck;
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struct {
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struct drm_i915_gem_object *obj;
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u32 gtt_offset;
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volatile u32 *cpu_page;
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} scratch;
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bool needs_cmd_parser;
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/*
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* Table of commands the command parser needs to know about
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* for this ring.
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*/
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DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER);
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/*
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* Table of registers allowed in commands that read/write registers.
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*/
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const u32 *reg_table;
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int reg_count;
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/*
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* Table of registers allowed in commands that read/write registers, but
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* only from the DRM master.
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*/
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const u32 *master_reg_table;
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int master_reg_count;
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/*
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* Returns the bitmask for the length field of the specified command.
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* Return 0 for an unrecognized/invalid command.
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*
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* If the command parser finds an entry for a command in the ring's
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* cmd_tables, it gets the command's length based on the table entry.
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* If not, it calls this function to determine the per-ring length field
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* encoding for the command (i.e. certain opcode ranges use certain bits
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* to encode the command length in the header).
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*/
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u32 (*get_cmd_length_mask)(u32 cmd_header);
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};
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bool intel_ring_initialized(struct intel_engine_cs *ring);
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static inline unsigned
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intel_ring_flag(struct intel_engine_cs *ring)
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{
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return 1 << ring->id;
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}
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static inline u32
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intel_ring_sync_index(struct intel_engine_cs *ring,
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struct intel_engine_cs *other)
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{
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int idx;
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/*
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* rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
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* vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
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* bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
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* vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
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* vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
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*/
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idx = (other - ring) - 1;
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if (idx < 0)
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idx += I915_NUM_RINGS;
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return idx;
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}
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static inline u32
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intel_read_status_page(struct intel_engine_cs *ring,
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int reg)
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{
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/* Ensure that the compiler doesn't optimize away the load. */
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barrier();
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return ring->status_page.page_addr[reg];
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}
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static inline void
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intel_write_status_page(struct intel_engine_cs *ring,
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int reg, u32 value)
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{
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ring->status_page.page_addr[reg] = value;
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}
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/**
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* Reads a dword out of the status page, which is written to from the command
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* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
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* MI_STORE_DATA_IMM.
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*
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* The following dwords have a reserved meaning:
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* 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
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* 0x04: ring 0 head pointer
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* 0x05: ring 1 head pointer (915-class)
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* 0x06: ring 2 head pointer (915-class)
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* 0x10-0x1b: Context status DWords (GM45)
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* 0x1f: Last written status offset. (GM45)
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*
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* The area from dword 0x20 to 0x3ff is available for driver usage.
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*/
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#define I915_GEM_HWS_INDEX 0x20
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#define I915_GEM_HWS_SCRATCH_INDEX 0x30
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#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
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void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
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int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
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struct intel_ringbuffer *ringbuf);
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void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
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int intel_alloc_ringbuffer_obj(struct drm_device *dev,
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struct intel_ringbuffer *ringbuf);
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void intel_stop_ring_buffer(struct intel_engine_cs *ring);
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void intel_cleanup_ring_buffer(struct intel_engine_cs *ring);
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int __must_check intel_ring_begin(struct intel_engine_cs *ring, int n);
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int __must_check intel_ring_cacheline_align(struct intel_engine_cs *ring);
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static inline void intel_ring_emit(struct intel_engine_cs *ring,
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u32 data)
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{
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struct intel_ringbuffer *ringbuf = ring->buffer;
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iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
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ringbuf->tail += 4;
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}
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static inline void intel_ring_advance(struct intel_engine_cs *ring)
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{
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struct intel_ringbuffer *ringbuf = ring->buffer;
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ringbuf->tail &= ringbuf->size - 1;
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}
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int __intel_ring_space(int head, int tail, int size);
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void intel_ring_update_space(struct intel_ringbuffer *ringbuf);
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int intel_ring_space(struct intel_ringbuffer *ringbuf);
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bool intel_ring_stopped(struct intel_engine_cs *ring);
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void __intel_ring_advance(struct intel_engine_cs *ring);
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int __must_check intel_ring_idle(struct intel_engine_cs *ring);
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void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno);
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int intel_ring_flush_all_caches(struct intel_engine_cs *ring);
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int intel_ring_invalidate_all_caches(struct intel_engine_cs *ring);
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void intel_fini_pipe_control(struct intel_engine_cs *ring);
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int intel_init_pipe_control(struct intel_engine_cs *ring);
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int intel_init_render_ring_buffer(struct drm_device *dev);
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int intel_init_bsd_ring_buffer(struct drm_device *dev);
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int intel_init_bsd2_ring_buffer(struct drm_device *dev);
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int intel_init_blt_ring_buffer(struct drm_device *dev);
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int intel_init_vebox_ring_buffer(struct drm_device *dev);
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u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
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void intel_ring_setup_status_page(struct intel_engine_cs *ring);
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int init_workarounds_ring(struct intel_engine_cs *ring);
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static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
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{
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return ringbuf->tail;
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}
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static inline struct drm_i915_gem_request *
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intel_ring_get_request(struct intel_engine_cs *ring)
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{
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BUG_ON(ring->outstanding_lazy_request == NULL);
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return ring->outstanding_lazy_request;
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}
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#endif /* _INTEL_RINGBUFFER_H_ */
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