133 lines
3.1 KiB
Makefile
133 lines
3.1 KiB
Makefile
###
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# Main build makefile.
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#
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# Lots of this code have been borrowed or heavily inspired from parts
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# of kbuild code, which is not credited, but mostly developed by:
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#
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# Copyright (C) Sam Ravnborg <sam@mars.ravnborg.org>, 2015
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# Copyright (C) Linus Torvalds <torvalds@linux-foundation.org>, 2015
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#
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PHONY := __build
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__build:
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ifeq ($(V),1)
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quiet =
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Q =
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else
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quiet=quiet_
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Q=@
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endif
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build-dir := $(srctree)/tools/build
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# Generic definitions
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include $(build-dir)/Build.include
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# do not force detected configuration
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-include $(OUTPUT).config-detected
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# Init all relevant variables used in build files so
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# 1) they have correct type
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# 2) they do not inherit any value from the environment
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subdir-y :=
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obj-y :=
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subdir-y :=
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subdir-obj-y :=
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# Build definitions
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build-file := $(dir)/Build
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-include $(build-file)
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quiet_cmd_flex = FLEX $@
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quiet_cmd_bison = BISON $@
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# Create directory unless it exists
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quiet_cmd_mkdir = MKDIR $(dir $@)
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cmd_mkdir = mkdir -p $(dir $@)
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rule_mkdir = $(if $(wildcard $(dir $@)),,@$(call echo-cmd,mkdir) $(cmd_mkdir))
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# Compile command
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quiet_cmd_cc_o_c = CC $@
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cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $<
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quiet_cmd_cc_i_c = CPP $@
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cmd_cc_i_c = $(CC) $(c_flags) -E -o $@ $<
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quiet_cmd_cc_s_c = AS $@
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cmd_cc_s_c = $(CC) $(c_flags) -S -o $@ $<
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quiet_cmd_gen = GEN $@
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# Link agregate command
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# If there's nothing to link, create empty $@ object.
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quiet_cmd_ld_multi = LD $@
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cmd_ld_multi = $(if $(strip $(obj-y)),\
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$(LD) -r -o $@ $(filter $(obj-y),$^),rm -f $@; $(AR) rcs $@)
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# Build rules
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$(OUTPUT)%.o: %.c FORCE
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$(call rule_mkdir)
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$(call if_changed_dep,cc_o_c)
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$(OUTPUT)%.o: %.S FORCE
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$(call rule_mkdir)
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$(call if_changed_dep,cc_o_c)
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$(OUTPUT)%.i: %.c FORCE
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$(call rule_mkdir)
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$(call if_changed_dep,cc_i_c)
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$(OUTPUT)%.i: %.S FORCE
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$(call rule_mkdir)
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$(call if_changed_dep,cc_i_c)
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$(OUTPUT)%.s: %.c FORCE
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$(call rule_mkdir)
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$(call if_changed_dep,cc_s_c)
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# Gather build data:
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# obj-y - list of build objects
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# subdir-y - list of directories to nest
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# subdir-obj-y - list of directories objects 'dir/$(obj)-in.o'
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obj-y := $($(obj)-y)
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subdir-y := $(patsubst %/,%,$(filter %/, $(obj-y)))
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obj-y := $(patsubst %/, %/$(obj)-in.o, $(obj-y))
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subdir-obj-y := $(filter %/$(obj)-in.o, $(obj-y))
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# '$(OUTPUT)/dir' prefix to all objects
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objprefix := $(subst ./,,$(OUTPUT)$(dir)/)
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obj-y := $(addprefix $(objprefix),$(obj-y))
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subdir-obj-y := $(addprefix $(objprefix),$(subdir-obj-y))
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# Final '$(obj)-in.o' object
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in-target := $(objprefix)$(obj)-in.o
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PHONY += $(subdir-y)
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$(subdir-y):
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$(Q)$(MAKE) -f $(build-dir)/Makefile.build dir=$(dir)/$@ obj=$(obj)
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$(sort $(subdir-obj-y)): $(subdir-y) ;
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$(in-target): $(obj-y) FORCE
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$(call rule_mkdir)
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$(call if_changed,ld_multi)
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__build: $(in-target)
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@:
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PHONY += FORCE
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FORCE:
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# Include all cmd files to get all the dependency rules
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# for all objects included
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targets := $(wildcard $(sort $(obj-y) $(in-target) $(MAKECMDGOALS)))
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cmd_files := $(wildcard $(foreach f,$(targets),$(dir $(f)).$(notdir $(f)).cmd))
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ifneq ($(cmd_files),)
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include $(cmd_files)
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endif
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.PHONY: $(PHONY)
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