160 lines
3.9 KiB
C
160 lines
3.9 KiB
C
/*
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* Copyright (C) 2009 Thomas Gleixner <tglx@linutronix.de>
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*
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* For licencing details see kernel-base/COPYING
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*/
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/export.h>
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#include <linux/pci.h>
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#include <asm/acpi.h>
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#include <asm/bios_ebda.h>
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#include <asm/paravirt.h>
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#include <asm/pci_x86.h>
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#include <asm/mpspec.h>
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#include <asm/setup.h>
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#include <asm/apic.h>
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#include <asm/e820/api.h>
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#include <asm/time.h>
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#include <asm/irq.h>
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#include <asm/io_apic.h>
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#include <asm/hpet.h>
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#include <asm/pat.h>
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#include <asm/tsc.h>
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#include <asm/iommu.h>
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#include <asm/mach_traps.h>
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void x86_init_noop(void) { }
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void __init x86_init_uint_noop(unsigned int unused) { }
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static int __init iommu_init_noop(void) { return 0; }
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static void iommu_shutdown_noop(void) { }
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static bool __init bool_x86_init_noop(void) { return false; }
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static void x86_op_int_noop(int cpu) { }
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/*
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* The platform setup functions are preset with the default functions
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* for standard PC hardware.
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*/
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struct x86_init_ops x86_init __initdata = {
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.resources = {
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.probe_roms = probe_roms,
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.reserve_resources = reserve_standard_io_resources,
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.memory_setup = e820__memory_setup_default,
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},
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.mpparse = {
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.mpc_record = x86_init_uint_noop,
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.setup_ioapic_ids = x86_init_noop,
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.mpc_apic_id = default_mpc_apic_id,
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.smp_read_mpc_oem = default_smp_read_mpc_oem,
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.mpc_oem_bus_info = default_mpc_oem_bus_info,
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.find_smp_config = default_find_smp_config,
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.get_smp_config = default_get_smp_config,
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},
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.irqs = {
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.pre_vector_init = init_ISA_irqs,
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.intr_init = native_init_IRQ,
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.trap_init = x86_init_noop,
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.intr_mode_init = apic_intr_mode_init
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},
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.oem = {
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.arch_setup = x86_init_noop,
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.banner = default_banner,
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},
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.paging = {
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.pagetable_init = native_pagetable_init,
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},
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.timers = {
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.setup_percpu_clockev = setup_boot_APIC_clock,
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.timer_init = hpet_time_init,
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.wallclock_init = x86_init_noop,
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},
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.iommu = {
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.iommu_init = iommu_init_noop,
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},
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.pci = {
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.init = x86_default_pci_init,
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.init_irq = x86_default_pci_init_irq,
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.fixup_irqs = x86_default_pci_fixup_irqs,
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},
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.hyper = {
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.init_platform = x86_init_noop,
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.guest_late_init = x86_init_noop,
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.x2apic_available = bool_x86_init_noop,
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.init_mem_mapping = x86_init_noop,
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.init_after_bootmem = x86_init_noop,
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},
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.acpi = {
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.get_root_pointer = x86_default_get_root_pointer,
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.reduced_hw_early_init = acpi_generic_reduced_hw_init,
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},
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};
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struct x86_cpuinit_ops x86_cpuinit = {
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.early_percpu_clock_init = x86_init_noop,
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.setup_percpu_clockev = setup_secondary_APIC_clock,
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};
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static void default_nmi_init(void) { };
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struct x86_platform_ops x86_platform __ro_after_init = {
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.calibrate_cpu = native_calibrate_cpu_early,
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.calibrate_tsc = native_calibrate_tsc,
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.get_wallclock = mach_get_cmos_time,
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.set_wallclock = mach_set_rtc_mmss,
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.iommu_shutdown = iommu_shutdown_noop,
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.is_untracked_pat_range = is_ISA_range,
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.nmi_init = default_nmi_init,
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.get_nmi_reason = default_get_nmi_reason,
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.save_sched_clock_state = tsc_save_sched_clock_state,
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.restore_sched_clock_state = tsc_restore_sched_clock_state,
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.hyper.pin_vcpu = x86_op_int_noop,
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};
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EXPORT_SYMBOL_GPL(x86_platform);
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#if defined(CONFIG_PCI_MSI)
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struct x86_msi_ops x86_msi __ro_after_init = {
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.setup_msi_irqs = native_setup_msi_irqs,
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.teardown_msi_irq = native_teardown_msi_irq,
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.teardown_msi_irqs = default_teardown_msi_irqs,
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.restore_msi_irqs = default_restore_msi_irqs,
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};
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/* MSI arch specific hooks */
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int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
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{
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return x86_msi.setup_msi_irqs(dev, nvec, type);
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}
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void arch_teardown_msi_irqs(struct pci_dev *dev)
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{
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x86_msi.teardown_msi_irqs(dev);
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}
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void arch_teardown_msi_irq(unsigned int irq)
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{
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x86_msi.teardown_msi_irq(irq);
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}
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void arch_restore_msi_irqs(struct pci_dev *dev)
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{
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x86_msi.restore_msi_irqs(dev);
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}
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#endif
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struct x86_apic_ops x86_apic_ops __ro_after_init = {
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.io_apic_read = native_io_apic_read,
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.restore = native_restore_boot_irq_mode,
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};
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