432 lines
11 KiB
C
432 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Universal Flash Storage Host controller Platform bus based glue driver
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* Copyright (C) 2011-2013 Samsung India Software Operations
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*
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* Authors:
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* Santosh Yaraganavi <santosh.sy@samsung.com>
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* Vinayak Holikatti <h.vinayak@samsung.com>
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*/
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include "ufshcd.h"
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#include "ufshcd-pltfrm.h"
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#include "unipro.h"
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#define UFSHCD_DEFAULT_LANES_PER_DIRECTION 2
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static int ufshcd_parse_clock_info(struct ufs_hba *hba)
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{
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int ret = 0;
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int cnt;
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int i;
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struct device *dev = hba->dev;
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struct device_node *np = dev->of_node;
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char *name;
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u32 *clkfreq = NULL;
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struct ufs_clk_info *clki;
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int len = 0;
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size_t sz = 0;
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if (!np)
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goto out;
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cnt = of_property_count_strings(np, "clock-names");
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if (!cnt || (cnt == -EINVAL)) {
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dev_info(dev, "%s: Unable to find clocks, assuming enabled\n",
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__func__);
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} else if (cnt < 0) {
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dev_err(dev, "%s: count clock strings failed, err %d\n",
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__func__, cnt);
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ret = cnt;
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}
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if (cnt <= 0)
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goto out;
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if (!of_get_property(np, "freq-table-hz", &len)) {
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dev_info(dev, "freq-table-hz property not specified\n");
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goto out;
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}
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if (len <= 0)
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goto out;
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sz = len / sizeof(*clkfreq);
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if (sz != 2 * cnt) {
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dev_err(dev, "%s len mismatch\n", "freq-table-hz");
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ret = -EINVAL;
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goto out;
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}
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clkfreq = devm_kcalloc(dev, sz, sizeof(*clkfreq),
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GFP_KERNEL);
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if (!clkfreq) {
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ret = -ENOMEM;
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goto out;
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}
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ret = of_property_read_u32_array(np, "freq-table-hz",
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clkfreq, sz);
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if (ret && (ret != -EINVAL)) {
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dev_err(dev, "%s: error reading array %d\n",
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"freq-table-hz", ret);
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return ret;
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}
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for (i = 0; i < sz; i += 2) {
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ret = of_property_read_string_index(np,
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"clock-names", i/2, (const char **)&name);
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if (ret)
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goto out;
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clki = devm_kzalloc(dev, sizeof(*clki), GFP_KERNEL);
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if (!clki) {
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ret = -ENOMEM;
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goto out;
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}
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clki->min_freq = clkfreq[i];
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clki->max_freq = clkfreq[i+1];
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clki->name = kstrdup(name, GFP_KERNEL);
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if (!strcmp(name, "ref_clk"))
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clki->keep_link_active = true;
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dev_dbg(dev, "%s: min %u max %u name %s\n", "freq-table-hz",
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clki->min_freq, clki->max_freq, clki->name);
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list_add_tail(&clki->list, &hba->clk_list_head);
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}
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out:
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return ret;
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}
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#define MAX_PROP_SIZE 32
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static int ufshcd_populate_vreg(struct device *dev, const char *name,
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struct ufs_vreg **out_vreg)
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{
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int ret = 0;
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char prop_name[MAX_PROP_SIZE];
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struct ufs_vreg *vreg = NULL;
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struct device_node *np = dev->of_node;
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if (!np) {
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dev_err(dev, "%s: non DT initialization\n", __func__);
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goto out;
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}
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snprintf(prop_name, MAX_PROP_SIZE, "%s-supply", name);
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if (!of_parse_phandle(np, prop_name, 0)) {
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dev_info(dev, "%s: Unable to find %s regulator, assuming enabled\n",
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__func__, prop_name);
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goto out;
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}
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vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
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if (!vreg)
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return -ENOMEM;
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vreg->name = kstrdup(name, GFP_KERNEL);
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snprintf(prop_name, MAX_PROP_SIZE, "%s-max-microamp", name);
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if (of_property_read_u32(np, prop_name, &vreg->max_uA)) {
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dev_info(dev, "%s: unable to find %s\n", __func__, prop_name);
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vreg->max_uA = 0;
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}
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out:
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if (!ret)
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*out_vreg = vreg;
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return ret;
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}
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/**
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* ufshcd_parse_regulator_info - get regulator info from device tree
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* @hba: per adapter instance
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*
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* Get regulator info from device tree for vcc, vccq, vccq2 power supplies.
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* If any of the supplies are not defined it is assumed that they are always-on
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* and hence return zero. If the property is defined but parsing is failed
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* then return corresponding error.
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*/
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static int ufshcd_parse_regulator_info(struct ufs_hba *hba)
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{
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int err;
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struct device *dev = hba->dev;
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struct ufs_vreg_info *info = &hba->vreg_info;
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err = ufshcd_populate_vreg(dev, "vdd-hba", &info->vdd_hba);
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if (err)
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goto out;
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err = ufshcd_populate_vreg(dev, "vcc", &info->vcc);
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if (err)
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goto out;
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err = ufshcd_populate_vreg(dev, "vccq", &info->vccq);
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if (err)
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goto out;
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err = ufshcd_populate_vreg(dev, "vccq2", &info->vccq2);
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out:
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return err;
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}
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#ifdef CONFIG_PM
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/**
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* ufshcd_pltfrm_suspend - suspend power management function
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* @dev: pointer to device handle
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*
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* Returns 0 if successful
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* Returns non-zero otherwise
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*/
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int ufshcd_pltfrm_suspend(struct device *dev)
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{
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return ufshcd_system_suspend(dev_get_drvdata(dev));
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}
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EXPORT_SYMBOL_GPL(ufshcd_pltfrm_suspend);
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/**
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* ufshcd_pltfrm_resume - resume power management function
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* @dev: pointer to device handle
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*
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* Returns 0 if successful
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* Returns non-zero otherwise
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*/
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int ufshcd_pltfrm_resume(struct device *dev)
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{
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return ufshcd_system_resume(dev_get_drvdata(dev));
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}
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EXPORT_SYMBOL_GPL(ufshcd_pltfrm_resume);
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int ufshcd_pltfrm_runtime_suspend(struct device *dev)
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{
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return ufshcd_runtime_suspend(dev_get_drvdata(dev));
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}
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EXPORT_SYMBOL_GPL(ufshcd_pltfrm_runtime_suspend);
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int ufshcd_pltfrm_runtime_resume(struct device *dev)
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{
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return ufshcd_runtime_resume(dev_get_drvdata(dev));
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}
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EXPORT_SYMBOL_GPL(ufshcd_pltfrm_runtime_resume);
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int ufshcd_pltfrm_runtime_idle(struct device *dev)
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{
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return ufshcd_runtime_idle(dev_get_drvdata(dev));
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}
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EXPORT_SYMBOL_GPL(ufshcd_pltfrm_runtime_idle);
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#endif /* CONFIG_PM */
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void ufshcd_pltfrm_shutdown(struct platform_device *pdev)
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{
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ufshcd_shutdown((struct ufs_hba *)platform_get_drvdata(pdev));
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}
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EXPORT_SYMBOL_GPL(ufshcd_pltfrm_shutdown);
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static void ufshcd_init_lanes_per_dir(struct ufs_hba *hba)
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{
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struct device *dev = hba->dev;
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int ret;
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ret = of_property_read_u32(dev->of_node, "lanes-per-direction",
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&hba->lanes_per_direction);
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if (ret) {
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dev_dbg(hba->dev,
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"%s: failed to read lanes-per-direction, ret=%d\n",
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__func__, ret);
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hba->lanes_per_direction = UFSHCD_DEFAULT_LANES_PER_DIRECTION;
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}
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}
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/**
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* ufshcd_get_pwr_dev_param - get finally agreed attributes for
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* power mode change
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* @pltfrm_param: pointer to platform parameters
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* @dev_max: pointer to device attributes
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* @agreed_pwr: returned agreed attributes
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*
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* Returns 0 on success, non-zero value on failure
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*/
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int ufshcd_get_pwr_dev_param(struct ufs_dev_params *pltfrm_param,
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struct ufs_pa_layer_attr *dev_max,
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struct ufs_pa_layer_attr *agreed_pwr)
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{
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int min_pltfrm_gear;
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int min_dev_gear;
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bool is_dev_sup_hs = false;
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bool is_pltfrm_max_hs = false;
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if (dev_max->pwr_rx == FAST_MODE)
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is_dev_sup_hs = true;
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if (pltfrm_param->desired_working_mode == UFS_HS_MODE) {
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is_pltfrm_max_hs = true;
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min_pltfrm_gear = min_t(u32, pltfrm_param->hs_rx_gear,
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pltfrm_param->hs_tx_gear);
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} else {
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min_pltfrm_gear = min_t(u32, pltfrm_param->pwm_rx_gear,
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pltfrm_param->pwm_tx_gear);
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}
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/*
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* device doesn't support HS but
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* pltfrm_param->desired_working_mode is HS,
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* thus device and pltfrm_param don't agree
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*/
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if (!is_dev_sup_hs && is_pltfrm_max_hs) {
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pr_info("%s: device doesn't support HS\n",
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__func__);
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return -ENOTSUPP;
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} else if (is_dev_sup_hs && is_pltfrm_max_hs) {
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/*
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* since device supports HS, it supports FAST_MODE.
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* since pltfrm_param->desired_working_mode is also HS
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* then final decision (FAST/FASTAUTO) is done according
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* to pltfrm_params as it is the restricting factor
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*/
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agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_hs;
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agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
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} else {
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/*
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* here pltfrm_param->desired_working_mode is PWM.
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* it doesn't matter whether device supports HS or PWM,
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* in both cases pltfrm_param->desired_working_mode will
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* determine the mode
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*/
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agreed_pwr->pwr_rx = pltfrm_param->rx_pwr_pwm;
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agreed_pwr->pwr_tx = agreed_pwr->pwr_rx;
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}
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/*
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* we would like tx to work in the minimum number of lanes
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* between device capability and vendor preferences.
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* the same decision will be made for rx
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*/
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agreed_pwr->lane_tx = min_t(u32, dev_max->lane_tx,
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pltfrm_param->tx_lanes);
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agreed_pwr->lane_rx = min_t(u32, dev_max->lane_rx,
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pltfrm_param->rx_lanes);
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/* device maximum gear is the minimum between device rx and tx gears */
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min_dev_gear = min_t(u32, dev_max->gear_rx, dev_max->gear_tx);
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/*
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* if both device capabilities and vendor pre-defined preferences are
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* both HS or both PWM then set the minimum gear to be the chosen
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* working gear.
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* if one is PWM and one is HS then the one that is PWM get to decide
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* what is the gear, as it is the one that also decided previously what
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* pwr the device will be configured to.
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*/
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if ((is_dev_sup_hs && is_pltfrm_max_hs) ||
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(!is_dev_sup_hs && !is_pltfrm_max_hs)) {
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agreed_pwr->gear_rx =
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min_t(u32, min_dev_gear, min_pltfrm_gear);
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} else if (!is_dev_sup_hs) {
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agreed_pwr->gear_rx = min_dev_gear;
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} else {
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agreed_pwr->gear_rx = min_pltfrm_gear;
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}
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agreed_pwr->gear_tx = agreed_pwr->gear_rx;
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agreed_pwr->hs_rate = pltfrm_param->hs_rate;
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return 0;
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}
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EXPORT_SYMBOL_GPL(ufshcd_get_pwr_dev_param);
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void ufshcd_init_pwr_dev_param(struct ufs_dev_params *dev_param)
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{
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dev_param->tx_lanes = 2;
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dev_param->rx_lanes = 2;
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dev_param->hs_rx_gear = UFS_HS_G3;
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dev_param->hs_tx_gear = UFS_HS_G3;
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dev_param->pwm_rx_gear = UFS_PWM_G4;
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dev_param->pwm_tx_gear = UFS_PWM_G4;
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dev_param->rx_pwr_pwm = SLOW_MODE;
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dev_param->tx_pwr_pwm = SLOW_MODE;
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dev_param->rx_pwr_hs = FAST_MODE;
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dev_param->tx_pwr_hs = FAST_MODE;
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dev_param->hs_rate = PA_HS_MODE_B;
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dev_param->desired_working_mode = UFS_HS_MODE;
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}
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EXPORT_SYMBOL_GPL(ufshcd_init_pwr_dev_param);
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/**
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* ufshcd_pltfrm_init - probe routine of the driver
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* @pdev: pointer to Platform device handle
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* @vops: pointer to variant ops
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*
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* Returns 0 on success, non-zero value on failure
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*/
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int ufshcd_pltfrm_init(struct platform_device *pdev,
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const struct ufs_hba_variant_ops *vops)
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{
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struct ufs_hba *hba;
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void __iomem *mmio_base;
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int irq, err;
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struct device *dev = &pdev->dev;
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mmio_base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(mmio_base)) {
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err = PTR_ERR(mmio_base);
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goto out;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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err = -ENODEV;
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goto out;
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}
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err = ufshcd_alloc_host(dev, &hba);
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if (err) {
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dev_err(&pdev->dev, "Allocation failed\n");
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goto out;
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}
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hba->vops = vops;
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err = ufshcd_parse_clock_info(hba);
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if (err) {
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dev_err(&pdev->dev, "%s: clock parse failed %d\n",
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__func__, err);
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goto dealloc_host;
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}
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err = ufshcd_parse_regulator_info(hba);
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if (err) {
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dev_err(&pdev->dev, "%s: regulator init failed %d\n",
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__func__, err);
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goto dealloc_host;
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}
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ufshcd_init_lanes_per_dir(hba);
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err = ufshcd_init(hba, mmio_base, irq);
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if (err) {
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dev_err(dev, "Initialization failed\n");
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goto dealloc_host;
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}
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platform_set_drvdata(pdev, hba);
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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return 0;
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dealloc_host:
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ufshcd_dealloc_host(hba);
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out:
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return err;
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}
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EXPORT_SYMBOL_GPL(ufshcd_pltfrm_init);
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MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>");
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MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>");
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MODULE_DESCRIPTION("UFS host controller Platform bus based glue driver");
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MODULE_LICENSE("GPL");
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MODULE_VERSION(UFSHCD_DRIVER_VERSION);
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