424 lines
11 KiB
C
424 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* STM32 Timer Encoder and Counter driver
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*
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* Copyright (C) STMicroelectronics 2018
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*
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* Author: Benjamin Gaignard <benjamin.gaignard@st.com>
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*
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*/
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#include <linux/counter.h>
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#include <linux/mfd/stm32-timers.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#define TIM_CCMR_CCXS (BIT(8) | BIT(0))
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#define TIM_CCMR_MASK (TIM_CCMR_CC1S | TIM_CCMR_CC2S | \
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TIM_CCMR_IC1F | TIM_CCMR_IC2F)
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#define TIM_CCER_MASK (TIM_CCER_CC1P | TIM_CCER_CC1NP | \
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TIM_CCER_CC2P | TIM_CCER_CC2NP)
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struct stm32_timer_regs {
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u32 cr1;
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u32 cnt;
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u32 smcr;
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u32 arr;
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};
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struct stm32_timer_cnt {
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struct regmap *regmap;
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struct clk *clk;
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u32 max_arr;
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bool enabled;
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struct stm32_timer_regs bak;
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};
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static const enum counter_function stm32_count_functions[] = {
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COUNTER_FUNCTION_INCREASE,
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COUNTER_FUNCTION_QUADRATURE_X2_A,
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COUNTER_FUNCTION_QUADRATURE_X2_B,
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COUNTER_FUNCTION_QUADRATURE_X4,
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};
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static int stm32_count_read(struct counter_device *counter,
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struct counter_count *count, u64 *val)
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{
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struct stm32_timer_cnt *const priv = counter_priv(counter);
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u32 cnt;
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regmap_read(priv->regmap, TIM_CNT, &cnt);
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*val = cnt;
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return 0;
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}
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static int stm32_count_write(struct counter_device *counter,
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struct counter_count *count, const u64 val)
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{
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struct stm32_timer_cnt *const priv = counter_priv(counter);
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u32 ceiling;
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regmap_read(priv->regmap, TIM_ARR, &ceiling);
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if (val > ceiling)
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return -EINVAL;
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return regmap_write(priv->regmap, TIM_CNT, val);
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}
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static int stm32_count_function_read(struct counter_device *counter,
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struct counter_count *count,
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enum counter_function *function)
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{
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struct stm32_timer_cnt *const priv = counter_priv(counter);
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u32 smcr;
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regmap_read(priv->regmap, TIM_SMCR, &smcr);
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switch (smcr & TIM_SMCR_SMS) {
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case TIM_SMCR_SMS_SLAVE_MODE_DISABLED:
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*function = COUNTER_FUNCTION_INCREASE;
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return 0;
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case TIM_SMCR_SMS_ENCODER_MODE_1:
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*function = COUNTER_FUNCTION_QUADRATURE_X2_A;
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return 0;
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case TIM_SMCR_SMS_ENCODER_MODE_2:
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*function = COUNTER_FUNCTION_QUADRATURE_X2_B;
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return 0;
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case TIM_SMCR_SMS_ENCODER_MODE_3:
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*function = COUNTER_FUNCTION_QUADRATURE_X4;
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return 0;
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default:
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return -EINVAL;
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}
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}
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static int stm32_count_function_write(struct counter_device *counter,
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struct counter_count *count,
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enum counter_function function)
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{
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struct stm32_timer_cnt *const priv = counter_priv(counter);
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u32 cr1, sms;
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switch (function) {
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case COUNTER_FUNCTION_INCREASE:
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sms = TIM_SMCR_SMS_SLAVE_MODE_DISABLED;
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break;
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case COUNTER_FUNCTION_QUADRATURE_X2_A:
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sms = TIM_SMCR_SMS_ENCODER_MODE_1;
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break;
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case COUNTER_FUNCTION_QUADRATURE_X2_B:
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sms = TIM_SMCR_SMS_ENCODER_MODE_2;
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break;
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case COUNTER_FUNCTION_QUADRATURE_X4:
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sms = TIM_SMCR_SMS_ENCODER_MODE_3;
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break;
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default:
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return -EINVAL;
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}
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/* Store enable status */
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regmap_read(priv->regmap, TIM_CR1, &cr1);
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
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regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
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/* Make sure that registers are updated */
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regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
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/* Restore the enable status */
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, cr1);
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return 0;
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}
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static int stm32_count_direction_read(struct counter_device *counter,
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struct counter_count *count,
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enum counter_count_direction *direction)
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{
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struct stm32_timer_cnt *const priv = counter_priv(counter);
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u32 cr1;
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regmap_read(priv->regmap, TIM_CR1, &cr1);
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*direction = (cr1 & TIM_CR1_DIR) ? COUNTER_COUNT_DIRECTION_BACKWARD :
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COUNTER_COUNT_DIRECTION_FORWARD;
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return 0;
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}
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static int stm32_count_ceiling_read(struct counter_device *counter,
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struct counter_count *count, u64 *ceiling)
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{
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struct stm32_timer_cnt *const priv = counter_priv(counter);
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u32 arr;
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regmap_read(priv->regmap, TIM_ARR, &arr);
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*ceiling = arr;
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return 0;
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}
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static int stm32_count_ceiling_write(struct counter_device *counter,
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struct counter_count *count, u64 ceiling)
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{
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struct stm32_timer_cnt *const priv = counter_priv(counter);
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if (ceiling > priv->max_arr)
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return -ERANGE;
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/* TIMx_ARR register shouldn't be buffered (ARPE=0) */
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
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regmap_write(priv->regmap, TIM_ARR, ceiling);
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return 0;
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}
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static int stm32_count_enable_read(struct counter_device *counter,
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struct counter_count *count, u8 *enable)
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{
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struct stm32_timer_cnt *const priv = counter_priv(counter);
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u32 cr1;
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regmap_read(priv->regmap, TIM_CR1, &cr1);
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*enable = cr1 & TIM_CR1_CEN;
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return 0;
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}
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static int stm32_count_enable_write(struct counter_device *counter,
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struct counter_count *count, u8 enable)
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{
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struct stm32_timer_cnt *const priv = counter_priv(counter);
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u32 cr1;
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if (enable) {
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regmap_read(priv->regmap, TIM_CR1, &cr1);
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if (!(cr1 & TIM_CR1_CEN))
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clk_enable(priv->clk);
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
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TIM_CR1_CEN);
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} else {
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regmap_read(priv->regmap, TIM_CR1, &cr1);
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
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if (cr1 & TIM_CR1_CEN)
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clk_disable(priv->clk);
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}
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/* Keep enabled state to properly handle low power states */
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priv->enabled = enable;
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return 0;
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}
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static struct counter_comp stm32_count_ext[] = {
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COUNTER_COMP_DIRECTION(stm32_count_direction_read),
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COUNTER_COMP_ENABLE(stm32_count_enable_read, stm32_count_enable_write),
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COUNTER_COMP_CEILING(stm32_count_ceiling_read,
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stm32_count_ceiling_write),
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};
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static const enum counter_synapse_action stm32_synapse_actions[] = {
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COUNTER_SYNAPSE_ACTION_NONE,
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COUNTER_SYNAPSE_ACTION_BOTH_EDGES
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};
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static int stm32_action_read(struct counter_device *counter,
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struct counter_count *count,
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struct counter_synapse *synapse,
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enum counter_synapse_action *action)
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{
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enum counter_function function;
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int err;
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err = stm32_count_function_read(counter, count, &function);
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if (err)
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return err;
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switch (function) {
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case COUNTER_FUNCTION_INCREASE:
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/* counts on internal clock when CEN=1 */
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*action = COUNTER_SYNAPSE_ACTION_NONE;
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return 0;
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case COUNTER_FUNCTION_QUADRATURE_X2_A:
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/* counts up/down on TI1FP1 edge depending on TI2FP2 level */
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if (synapse->signal->id == count->synapses[0].signal->id)
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*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
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else
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*action = COUNTER_SYNAPSE_ACTION_NONE;
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return 0;
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case COUNTER_FUNCTION_QUADRATURE_X2_B:
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/* counts up/down on TI2FP2 edge depending on TI1FP1 level */
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if (synapse->signal->id == count->synapses[1].signal->id)
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*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
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else
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*action = COUNTER_SYNAPSE_ACTION_NONE;
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return 0;
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case COUNTER_FUNCTION_QUADRATURE_X4:
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/* counts up/down on both TI1FP1 and TI2FP2 edges */
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*action = COUNTER_SYNAPSE_ACTION_BOTH_EDGES;
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return 0;
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default:
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return -EINVAL;
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}
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}
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static const struct counter_ops stm32_timer_cnt_ops = {
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.count_read = stm32_count_read,
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.count_write = stm32_count_write,
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.function_read = stm32_count_function_read,
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.function_write = stm32_count_function_write,
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.action_read = stm32_action_read,
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};
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static struct counter_signal stm32_signals[] = {
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{
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.id = 0,
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.name = "Channel 1 Quadrature A"
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},
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{
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.id = 1,
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.name = "Channel 1 Quadrature B"
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}
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};
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static struct counter_synapse stm32_count_synapses[] = {
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{
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.actions_list = stm32_synapse_actions,
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.num_actions = ARRAY_SIZE(stm32_synapse_actions),
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.signal = &stm32_signals[0]
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},
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{
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.actions_list = stm32_synapse_actions,
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.num_actions = ARRAY_SIZE(stm32_synapse_actions),
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.signal = &stm32_signals[1]
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}
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};
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static struct counter_count stm32_counts = {
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.id = 0,
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.name = "Channel 1 Count",
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.functions_list = stm32_count_functions,
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.num_functions = ARRAY_SIZE(stm32_count_functions),
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.synapses = stm32_count_synapses,
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.num_synapses = ARRAY_SIZE(stm32_count_synapses),
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.ext = stm32_count_ext,
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.num_ext = ARRAY_SIZE(stm32_count_ext)
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};
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static int stm32_timer_cnt_probe(struct platform_device *pdev)
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{
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struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
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struct device *dev = &pdev->dev;
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struct stm32_timer_cnt *priv;
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struct counter_device *counter;
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int ret;
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if (IS_ERR_OR_NULL(ddata))
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return -EINVAL;
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counter = devm_counter_alloc(dev, sizeof(*priv));
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if (!counter)
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return -ENOMEM;
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priv = counter_priv(counter);
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priv->regmap = ddata->regmap;
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priv->clk = ddata->clk;
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priv->max_arr = ddata->max_arr;
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counter->name = dev_name(dev);
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counter->parent = dev;
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counter->ops = &stm32_timer_cnt_ops;
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counter->counts = &stm32_counts;
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counter->num_counts = 1;
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counter->signals = stm32_signals;
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counter->num_signals = ARRAY_SIZE(stm32_signals);
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platform_set_drvdata(pdev, priv);
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/* Reset input selector to its default input */
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regmap_write(priv->regmap, TIM_TISEL, 0x0);
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/* Register Counter device */
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ret = devm_counter_add(dev, counter);
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if (ret < 0)
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dev_err_probe(dev, ret, "Failed to add counter\n");
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return ret;
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}
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static int __maybe_unused stm32_timer_cnt_suspend(struct device *dev)
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{
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struct stm32_timer_cnt *priv = dev_get_drvdata(dev);
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/* Only take care of enabled counter: don't disturb other MFD child */
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if (priv->enabled) {
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/* Backup registers that may get lost in low power mode */
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regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);
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regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);
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regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);
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regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);
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/* Disable the counter */
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
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clk_disable(priv->clk);
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}
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return pinctrl_pm_select_sleep_state(dev);
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}
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static int __maybe_unused stm32_timer_cnt_resume(struct device *dev)
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{
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struct stm32_timer_cnt *priv = dev_get_drvdata(dev);
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int ret;
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ret = pinctrl_pm_select_default_state(dev);
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if (ret)
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return ret;
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if (priv->enabled) {
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clk_enable(priv->clk);
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/* Restore registers that may have been lost */
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regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);
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regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);
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regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);
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/* Also re-enables the counter */
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regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);
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}
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(stm32_timer_cnt_pm_ops, stm32_timer_cnt_suspend,
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stm32_timer_cnt_resume);
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static const struct of_device_id stm32_timer_cnt_of_match[] = {
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{ .compatible = "st,stm32-timer-counter", },
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{},
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};
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MODULE_DEVICE_TABLE(of, stm32_timer_cnt_of_match);
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static struct platform_driver stm32_timer_cnt_driver = {
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.probe = stm32_timer_cnt_probe,
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.driver = {
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.name = "stm32-timer-counter",
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.of_match_table = stm32_timer_cnt_of_match,
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.pm = &stm32_timer_cnt_pm_ops,
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},
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};
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module_platform_driver(stm32_timer_cnt_driver);
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MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
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MODULE_ALIAS("platform:stm32-timer-counter");
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MODULE_DESCRIPTION("STMicroelectronics STM32 TIMER counter driver");
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MODULE_LICENSE("GPL v2");
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MODULE_IMPORT_NS(COUNTER);
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