480 lines
14 KiB
C
480 lines
14 KiB
C
/*
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* Copyright 2005 Stephane Marchesin.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __NOUVEAU_DRM_H__
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#define __NOUVEAU_DRM_H__
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#define DRM_NOUVEAU_EVENT_NVIF 0x80000000
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#include "drm.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#define NOUVEAU_GETPARAM_PCI_VENDOR 3
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#define NOUVEAU_GETPARAM_PCI_DEVICE 4
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#define NOUVEAU_GETPARAM_BUS_TYPE 5
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#define NOUVEAU_GETPARAM_FB_SIZE 8
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#define NOUVEAU_GETPARAM_AGP_SIZE 9
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#define NOUVEAU_GETPARAM_CHIPSET_ID 11
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#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
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#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
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#define NOUVEAU_GETPARAM_PTIMER_TIME 14
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#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
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#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
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/*
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* NOUVEAU_GETPARAM_EXEC_PUSH_MAX - query max pushes through getparam
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*
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* Query the maximum amount of IBs that can be pushed through a single
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* &drm_nouveau_exec structure and hence a single &DRM_IOCTL_NOUVEAU_EXEC
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* ioctl().
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*/
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#define NOUVEAU_GETPARAM_EXEC_PUSH_MAX 17
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struct drm_nouveau_getparam {
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__u64 param;
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__u64 value;
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};
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struct drm_nouveau_channel_alloc {
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__u32 fb_ctxdma_handle;
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__u32 tt_ctxdma_handle;
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__s32 channel;
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__u32 pushbuf_domains;
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/* Notifier memory */
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__u32 notifier_handle;
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/* DRM-enforced subchannel assignments */
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struct {
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__u32 handle;
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__u32 grclass;
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} subchan[8];
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__u32 nr_subchan;
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};
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struct drm_nouveau_channel_free {
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__s32 channel;
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};
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#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
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#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
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#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
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#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
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#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
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/* The BO will never be shared via import or export. */
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#define NOUVEAU_GEM_DOMAIN_NO_SHARE (1 << 5)
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#define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
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#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
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#define NOUVEAU_GEM_TILE_16BPP 0x00000001
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#define NOUVEAU_GEM_TILE_32BPP 0x00000002
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#define NOUVEAU_GEM_TILE_ZETA 0x00000004
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#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
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struct drm_nouveau_gem_info {
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__u32 handle;
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__u32 domain;
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__u64 size;
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__u64 offset;
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__u64 map_handle;
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__u32 tile_mode;
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__u32 tile_flags;
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};
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struct drm_nouveau_gem_new {
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struct drm_nouveau_gem_info info;
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__u32 channel_hint;
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__u32 align;
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};
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#define NOUVEAU_GEM_MAX_BUFFERS 1024
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struct drm_nouveau_gem_pushbuf_bo_presumed {
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__u32 valid;
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__u32 domain;
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__u64 offset;
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};
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struct drm_nouveau_gem_pushbuf_bo {
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__u64 user_priv;
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__u32 handle;
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__u32 read_domains;
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__u32 write_domains;
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__u32 valid_domains;
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struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
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};
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#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
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#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
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#define NOUVEAU_GEM_RELOC_OR (1 << 2)
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#define NOUVEAU_GEM_MAX_RELOCS 1024
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struct drm_nouveau_gem_pushbuf_reloc {
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__u32 reloc_bo_index;
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__u32 reloc_bo_offset;
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__u32 bo_index;
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__u32 flags;
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__u32 data;
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__u32 vor;
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__u32 tor;
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};
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#define NOUVEAU_GEM_MAX_PUSH 512
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struct drm_nouveau_gem_pushbuf_push {
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__u32 bo_index;
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__u32 pad;
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__u64 offset;
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__u64 length;
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#define NOUVEAU_GEM_PUSHBUF_NO_PREFETCH (1 << 23)
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};
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struct drm_nouveau_gem_pushbuf {
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__u32 channel;
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__u32 nr_buffers;
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__u64 buffers;
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__u32 nr_relocs;
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__u32 nr_push;
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__u64 relocs;
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__u64 push;
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__u32 suffix0;
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__u32 suffix1;
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#define NOUVEAU_GEM_PUSHBUF_SYNC (1ULL << 0)
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__u64 vram_available;
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__u64 gart_available;
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};
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#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
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#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
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struct drm_nouveau_gem_cpu_prep {
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__u32 handle;
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__u32 flags;
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};
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struct drm_nouveau_gem_cpu_fini {
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__u32 handle;
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};
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/**
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* struct drm_nouveau_sync - sync object
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*
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* This structure serves as synchronization mechanism for (potentially)
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* asynchronous operations such as EXEC or VM_BIND.
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*/
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struct drm_nouveau_sync {
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/**
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* @flags: the flags for a sync object
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*
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* The first 8 bits are used to determine the type of the sync object.
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*/
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__u32 flags;
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#define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0
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#define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1
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#define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf
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/**
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* @handle: the handle of the sync object
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*/
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__u32 handle;
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/**
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* @timeline_value:
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*
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* The timeline point of the sync object in case the syncobj is of
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* type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ.
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*/
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__u64 timeline_value;
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};
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/**
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* struct drm_nouveau_vm_init - GPU VA space init structure
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*
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* Used to initialize the GPU's VA space for a user client, telling the kernel
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* which portion of the VA space is managed by the UMD and kernel respectively.
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*
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* For the UMD to use the VM_BIND uAPI, this must be called before any BOs or
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* channels are created; if called afterwards DRM_IOCTL_NOUVEAU_VM_INIT fails
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* with -ENOSYS.
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*/
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struct drm_nouveau_vm_init {
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/**
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* @kernel_managed_addr: start address of the kernel managed VA space
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* region
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*/
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__u64 kernel_managed_addr;
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/**
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* @kernel_managed_size: size of the kernel managed VA space region in
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* bytes
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*/
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__u64 kernel_managed_size;
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};
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/**
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* struct drm_nouveau_vm_bind_op - VM_BIND operation
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*
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* This structure represents a single VM_BIND operation. UMDs should pass
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* an array of this structure via struct drm_nouveau_vm_bind's &op_ptr field.
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*/
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struct drm_nouveau_vm_bind_op {
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/**
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* @op: the operation type
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*/
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__u32 op;
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/**
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* @DRM_NOUVEAU_VM_BIND_OP_MAP:
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*
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* Map a GEM object to the GPU's VA space. Optionally, the
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* &DRM_NOUVEAU_VM_BIND_SPARSE flag can be passed to instruct the kernel to
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* create sparse mappings for the given range.
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*/
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#define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0
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/**
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* @DRM_NOUVEAU_VM_BIND_OP_UNMAP:
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*
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* Unmap an existing mapping in the GPU's VA space. If the region the mapping
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* is located in is a sparse region, new sparse mappings are created where the
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* unmapped (memory backed) mapping was mapped previously. To remove a sparse
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* region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set.
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*/
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#define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1
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/**
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* @flags: the flags for a &drm_nouveau_vm_bind_op
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*/
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__u32 flags;
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/**
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* @DRM_NOUVEAU_VM_BIND_SPARSE:
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*
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* Indicates that an allocated VA space region should be sparse.
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*/
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#define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8)
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/**
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* @handle: the handle of the DRM GEM object to map
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*/
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__u32 handle;
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/**
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* @pad: 32 bit padding, should be 0
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*/
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__u32 pad;
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/**
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* @addr:
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*
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* the address the VA space region or (memory backed) mapping should be mapped to
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*/
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__u64 addr;
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/**
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* @bo_offset: the offset within the BO backing the mapping
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*/
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__u64 bo_offset;
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/**
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* @range: the size of the requested mapping in bytes
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*/
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__u64 range;
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};
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/**
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* struct drm_nouveau_vm_bind - structure for DRM_IOCTL_NOUVEAU_VM_BIND
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*/
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struct drm_nouveau_vm_bind {
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/**
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* @op_count: the number of &drm_nouveau_vm_bind_op
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*/
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__u32 op_count;
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/**
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* @flags: the flags for a &drm_nouveau_vm_bind ioctl
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*/
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__u32 flags;
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/**
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* @DRM_NOUVEAU_VM_BIND_RUN_ASYNC:
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*
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* Indicates that the given VM_BIND operation should be executed asynchronously
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* by the kernel.
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*
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* If this flag is not supplied the kernel executes the associated operations
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* synchronously and doesn't accept any &drm_nouveau_sync objects.
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*/
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#define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1
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/**
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* @wait_count: the number of wait &drm_nouveau_syncs
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*/
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__u32 wait_count;
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/**
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* @sig_count: the number of &drm_nouveau_syncs to signal when finished
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*/
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__u32 sig_count;
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/**
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* @wait_ptr: pointer to &drm_nouveau_syncs to wait for
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*/
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__u64 wait_ptr;
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/**
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* @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
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*/
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__u64 sig_ptr;
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/**
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* @op_ptr: pointer to the &drm_nouveau_vm_bind_ops to execute
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*/
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__u64 op_ptr;
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};
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/**
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* struct drm_nouveau_exec_push - EXEC push operation
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*
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* This structure represents a single EXEC push operation. UMDs should pass an
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* array of this structure via struct drm_nouveau_exec's &push_ptr field.
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*/
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struct drm_nouveau_exec_push {
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/**
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* @va: the virtual address of the push buffer mapping
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*/
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__u64 va;
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/**
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* @va_len: the length of the push buffer mapping
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*/
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__u32 va_len;
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/**
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* @flags: the flags for this push buffer mapping
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*/
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__u32 flags;
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#define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1
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};
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/**
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* struct drm_nouveau_exec - structure for DRM_IOCTL_NOUVEAU_EXEC
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*/
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struct drm_nouveau_exec {
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/**
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* @channel: the channel to execute the push buffer in
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*/
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__u32 channel;
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/**
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* @push_count: the number of &drm_nouveau_exec_push ops
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*/
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__u32 push_count;
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/**
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* @wait_count: the number of wait &drm_nouveau_syncs
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*/
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__u32 wait_count;
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/**
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* @sig_count: the number of &drm_nouveau_syncs to signal when finished
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*/
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__u32 sig_count;
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/**
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* @wait_ptr: pointer to &drm_nouveau_syncs to wait for
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*/
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__u64 wait_ptr;
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/**
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* @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
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*/
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__u64 sig_ptr;
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/**
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* @push_ptr: pointer to &drm_nouveau_exec_push ops
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*/
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__u64 push_ptr;
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};
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#define DRM_NOUVEAU_GETPARAM 0x00
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#define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
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#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
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#define DRM_NOUVEAU_CHANNEL_FREE 0x03
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#define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
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#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
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#define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
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#define DRM_NOUVEAU_NVIF 0x07
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#define DRM_NOUVEAU_SVM_INIT 0x08
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#define DRM_NOUVEAU_SVM_BIND 0x09
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#define DRM_NOUVEAU_VM_INIT 0x10
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#define DRM_NOUVEAU_VM_BIND 0x11
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#define DRM_NOUVEAU_EXEC 0x12
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#define DRM_NOUVEAU_GEM_NEW 0x40
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#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
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#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
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#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
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#define DRM_NOUVEAU_GEM_INFO 0x44
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struct drm_nouveau_svm_init {
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__u64 unmanaged_addr;
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__u64 unmanaged_size;
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};
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struct drm_nouveau_svm_bind {
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__u64 header;
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__u64 va_start;
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__u64 va_end;
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__u64 npages;
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__u64 stride;
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__u64 result;
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__u64 reserved0;
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__u64 reserved1;
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};
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#define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0
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#define NOUVEAU_SVM_BIND_COMMAND_BITS 8
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#define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1)
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#define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8
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#define NOUVEAU_SVM_BIND_PRIORITY_BITS 8
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#define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1)
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#define NOUVEAU_SVM_BIND_TARGET_SHIFT 16
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#define NOUVEAU_SVM_BIND_TARGET_BITS 32
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#define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff
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/*
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* Below is use to validate ioctl argument, userspace can also use it to make
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* sure that no bit are set beyond known fields for a given kernel version.
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*/
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#define NOUVEAU_SVM_BIND_VALID_BITS 48
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#define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
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/*
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* NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory.
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* result: number of page successfuly migrate to the target memory.
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*/
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#define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0
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/*
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* NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory.
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*/
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#define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)
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#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
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#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
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#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
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#define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
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#define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
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#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
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#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
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#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
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#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
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#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
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#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init)
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#define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind)
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#define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec)
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __NOUVEAU_DRM_H__ */
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