1224 lines
29 KiB
C
1224 lines
29 KiB
C
#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/of_dma.h>
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#include <linux/of_irq.h>
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#include <linux/dmapool.h>
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#include <linux/interrupt.h>
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#include <linux/of_address.h>
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#include <linux/pm_runtime.h>
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#include "../dmaengine.h"
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#define DESC_TYPE 27
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#define DESC_TYPE_HOST 0x10
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#define DESC_TYPE_TEARD 0x13
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#define TD_DESC_IS_RX (1 << 16)
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#define TD_DESC_DMA_NUM 10
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#define DESC_LENGTH_BITS_NUM 21
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#define DESC_TYPE_USB (5 << 26)
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#define DESC_PD_COMPLETE (1 << 31)
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/* DMA engine */
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#define DMA_TDFDQ 4
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#define DMA_TXGCR(x) (0x800 + (x) * 0x20)
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#define DMA_RXGCR(x) (0x808 + (x) * 0x20)
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#define RXHPCRA0 4
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#define GCR_CHAN_ENABLE (1 << 31)
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#define GCR_TEARDOWN (1 << 30)
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#define GCR_STARV_RETRY (1 << 24)
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#define GCR_DESC_TYPE_HOST (1 << 14)
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/* DMA scheduler */
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#define DMA_SCHED_CTRL 0
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#define DMA_SCHED_CTRL_EN (1 << 31)
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#define DMA_SCHED_WORD(x) ((x) * 4 + 0x800)
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#define SCHED_ENTRY0_CHAN(x) ((x) << 0)
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#define SCHED_ENTRY0_IS_RX (1 << 7)
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#define SCHED_ENTRY1_CHAN(x) ((x) << 8)
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#define SCHED_ENTRY1_IS_RX (1 << 15)
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#define SCHED_ENTRY2_CHAN(x) ((x) << 16)
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#define SCHED_ENTRY2_IS_RX (1 << 23)
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#define SCHED_ENTRY3_CHAN(x) ((x) << 24)
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#define SCHED_ENTRY3_IS_RX (1 << 31)
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/* Queue manager */
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/* 4 KiB of memory for descriptors, 2 for each endpoint */
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#define ALLOC_DECS_NUM 128
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#define DESCS_AREAS 1
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#define TOTAL_DESCS_NUM (ALLOC_DECS_NUM * DESCS_AREAS)
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#define QMGR_SCRATCH_SIZE (TOTAL_DESCS_NUM * 4)
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#define QMGR_LRAM0_BASE 0x80
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#define QMGR_LRAM_SIZE 0x84
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#define QMGR_LRAM1_BASE 0x88
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#define QMGR_MEMBASE(x) (0x1000 + (x) * 0x10)
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#define QMGR_MEMCTRL(x) (0x1004 + (x) * 0x10)
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#define QMGR_MEMCTRL_IDX_SH 16
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#define QMGR_MEMCTRL_DESC_SH 8
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#define QMGR_PEND(x) (0x90 + (x) * 4)
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#define QMGR_PENDING_SLOT_Q(x) (x / 32)
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#define QMGR_PENDING_BIT_Q(x) (x % 32)
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#define QMGR_QUEUE_A(n) (0x2000 + (n) * 0x10)
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#define QMGR_QUEUE_B(n) (0x2004 + (n) * 0x10)
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#define QMGR_QUEUE_C(n) (0x2008 + (n) * 0x10)
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#define QMGR_QUEUE_D(n) (0x200c + (n) * 0x10)
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/* Packet Descriptor */
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#define PD2_ZERO_LENGTH (1 << 19)
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struct cppi41_channel {
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struct dma_chan chan;
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struct dma_async_tx_descriptor txd;
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struct cppi41_dd *cdd;
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struct cppi41_desc *desc;
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dma_addr_t desc_phys;
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void __iomem *gcr_reg;
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int is_tx;
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u32 residue;
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unsigned int q_num;
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unsigned int q_comp_num;
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unsigned int port_num;
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unsigned td_retry;
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unsigned td_queued:1;
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unsigned td_seen:1;
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unsigned td_desc_seen:1;
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struct list_head node; /* Node for pending list */
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};
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struct cppi41_desc {
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u32 pd0;
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u32 pd1;
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u32 pd2;
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u32 pd3;
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u32 pd4;
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u32 pd5;
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u32 pd6;
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u32 pd7;
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} __aligned(32);
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struct chan_queues {
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u16 submit;
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u16 complete;
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};
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struct cppi41_dd {
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struct dma_device ddev;
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void *qmgr_scratch;
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dma_addr_t scratch_phys;
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struct cppi41_desc *cd;
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dma_addr_t descs_phys;
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u32 first_td_desc;
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struct cppi41_channel *chan_busy[ALLOC_DECS_NUM];
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void __iomem *ctrl_mem;
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void __iomem *sched_mem;
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void __iomem *qmgr_mem;
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unsigned int irq;
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const struct chan_queues *queues_rx;
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const struct chan_queues *queues_tx;
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struct chan_queues td_queue;
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u16 first_completion_queue;
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u16 qmgr_num_pend;
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u32 n_chans;
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u8 platform;
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struct list_head pending; /* Pending queued transfers */
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spinlock_t lock; /* Lock for pending list */
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/* context for suspend/resume */
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unsigned int dma_tdfdq;
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bool is_suspended;
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};
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static struct chan_queues am335x_usb_queues_tx[] = {
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/* USB0 ENDP 1 */
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[ 0] = { .submit = 32, .complete = 93},
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[ 1] = { .submit = 34, .complete = 94},
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[ 2] = { .submit = 36, .complete = 95},
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[ 3] = { .submit = 38, .complete = 96},
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[ 4] = { .submit = 40, .complete = 97},
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[ 5] = { .submit = 42, .complete = 98},
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[ 6] = { .submit = 44, .complete = 99},
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[ 7] = { .submit = 46, .complete = 100},
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[ 8] = { .submit = 48, .complete = 101},
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[ 9] = { .submit = 50, .complete = 102},
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[10] = { .submit = 52, .complete = 103},
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[11] = { .submit = 54, .complete = 104},
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[12] = { .submit = 56, .complete = 105},
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[13] = { .submit = 58, .complete = 106},
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[14] = { .submit = 60, .complete = 107},
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/* USB1 ENDP1 */
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[15] = { .submit = 62, .complete = 125},
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[16] = { .submit = 64, .complete = 126},
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[17] = { .submit = 66, .complete = 127},
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[18] = { .submit = 68, .complete = 128},
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[19] = { .submit = 70, .complete = 129},
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[20] = { .submit = 72, .complete = 130},
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[21] = { .submit = 74, .complete = 131},
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[22] = { .submit = 76, .complete = 132},
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[23] = { .submit = 78, .complete = 133},
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[24] = { .submit = 80, .complete = 134},
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[25] = { .submit = 82, .complete = 135},
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[26] = { .submit = 84, .complete = 136},
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[27] = { .submit = 86, .complete = 137},
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[28] = { .submit = 88, .complete = 138},
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[29] = { .submit = 90, .complete = 139},
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};
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static const struct chan_queues am335x_usb_queues_rx[] = {
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/* USB0 ENDP 1 */
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[ 0] = { .submit = 1, .complete = 109},
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[ 1] = { .submit = 2, .complete = 110},
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[ 2] = { .submit = 3, .complete = 111},
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[ 3] = { .submit = 4, .complete = 112},
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[ 4] = { .submit = 5, .complete = 113},
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[ 5] = { .submit = 6, .complete = 114},
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[ 6] = { .submit = 7, .complete = 115},
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[ 7] = { .submit = 8, .complete = 116},
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[ 8] = { .submit = 9, .complete = 117},
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[ 9] = { .submit = 10, .complete = 118},
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[10] = { .submit = 11, .complete = 119},
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[11] = { .submit = 12, .complete = 120},
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[12] = { .submit = 13, .complete = 121},
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[13] = { .submit = 14, .complete = 122},
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[14] = { .submit = 15, .complete = 123},
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/* USB1 ENDP 1 */
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[15] = { .submit = 16, .complete = 141},
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[16] = { .submit = 17, .complete = 142},
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[17] = { .submit = 18, .complete = 143},
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[18] = { .submit = 19, .complete = 144},
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[19] = { .submit = 20, .complete = 145},
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[20] = { .submit = 21, .complete = 146},
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[21] = { .submit = 22, .complete = 147},
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[22] = { .submit = 23, .complete = 148},
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[23] = { .submit = 24, .complete = 149},
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[24] = { .submit = 25, .complete = 150},
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[25] = { .submit = 26, .complete = 151},
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[26] = { .submit = 27, .complete = 152},
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[27] = { .submit = 28, .complete = 153},
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[28] = { .submit = 29, .complete = 154},
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[29] = { .submit = 30, .complete = 155},
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};
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static const struct chan_queues da8xx_usb_queues_tx[] = {
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[0] = { .submit = 16, .complete = 24},
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[1] = { .submit = 18, .complete = 24},
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[2] = { .submit = 20, .complete = 24},
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[3] = { .submit = 22, .complete = 24},
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};
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static const struct chan_queues da8xx_usb_queues_rx[] = {
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[0] = { .submit = 1, .complete = 26},
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[1] = { .submit = 3, .complete = 26},
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[2] = { .submit = 5, .complete = 26},
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[3] = { .submit = 7, .complete = 26},
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};
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struct cppi_glue_infos {
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const struct chan_queues *queues_rx;
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const struct chan_queues *queues_tx;
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struct chan_queues td_queue;
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u16 first_completion_queue;
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u16 qmgr_num_pend;
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};
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static struct cppi41_channel *to_cpp41_chan(struct dma_chan *c)
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{
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return container_of(c, struct cppi41_channel, chan);
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}
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static struct cppi41_channel *desc_to_chan(struct cppi41_dd *cdd, u32 desc)
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{
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struct cppi41_channel *c;
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u32 descs_size;
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u32 desc_num;
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descs_size = sizeof(struct cppi41_desc) * ALLOC_DECS_NUM;
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if (!((desc >= cdd->descs_phys) &&
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(desc < (cdd->descs_phys + descs_size)))) {
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return NULL;
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}
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desc_num = (desc - cdd->descs_phys) / sizeof(struct cppi41_desc);
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BUG_ON(desc_num >= ALLOC_DECS_NUM);
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c = cdd->chan_busy[desc_num];
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cdd->chan_busy[desc_num] = NULL;
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/* Usecount for chan_busy[], paired with push_desc_queue() */
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pm_runtime_put(cdd->ddev.dev);
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return c;
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}
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static void cppi_writel(u32 val, void *__iomem *mem)
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{
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__raw_writel(val, mem);
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}
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static u32 cppi_readl(void *__iomem *mem)
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{
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return __raw_readl(mem);
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}
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static u32 pd_trans_len(u32 val)
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{
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return val & ((1 << (DESC_LENGTH_BITS_NUM + 1)) - 1);
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}
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static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num)
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{
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u32 desc;
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desc = cppi_readl(cdd->qmgr_mem + QMGR_QUEUE_D(queue_num));
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desc &= ~0x1f;
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return desc;
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}
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static irqreturn_t cppi41_irq(int irq, void *data)
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{
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struct cppi41_dd *cdd = data;
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u16 first_completion_queue = cdd->first_completion_queue;
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u16 qmgr_num_pend = cdd->qmgr_num_pend;
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struct cppi41_channel *c;
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int i;
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for (i = QMGR_PENDING_SLOT_Q(first_completion_queue); i < qmgr_num_pend;
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i++) {
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u32 val;
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u32 q_num;
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val = cppi_readl(cdd->qmgr_mem + QMGR_PEND(i));
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if (i == QMGR_PENDING_SLOT_Q(first_completion_queue) && val) {
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u32 mask;
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/* set corresponding bit for completetion Q 93 */
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mask = 1 << QMGR_PENDING_BIT_Q(first_completion_queue);
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/* not set all bits for queues less than Q 93 */
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mask--;
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/* now invert and keep only Q 93+ set */
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val &= ~mask;
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}
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if (val)
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__iormb();
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while (val) {
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u32 desc, len;
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/*
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* This should never trigger, see the comments in
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* push_desc_queue()
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*/
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WARN_ON(cdd->is_suspended);
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q_num = __fls(val);
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val &= ~(1 << q_num);
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q_num += 32 * i;
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desc = cppi41_pop_desc(cdd, q_num);
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c = desc_to_chan(cdd, desc);
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if (WARN_ON(!c)) {
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pr_err("%s() q %d desc %08x\n", __func__,
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q_num, desc);
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continue;
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}
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if (c->desc->pd2 & PD2_ZERO_LENGTH)
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len = 0;
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else
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len = pd_trans_len(c->desc->pd0);
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c->residue = pd_trans_len(c->desc->pd6) - len;
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dma_cookie_complete(&c->txd);
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dmaengine_desc_get_callback_invoke(&c->txd, NULL);
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}
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}
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return IRQ_HANDLED;
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}
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static dma_cookie_t cppi41_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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dma_cookie_t cookie;
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cookie = dma_cookie_assign(tx);
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return cookie;
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}
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static int cppi41_dma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct cppi41_channel *c = to_cpp41_chan(chan);
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struct cppi41_dd *cdd = c->cdd;
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int error;
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error = pm_runtime_get_sync(cdd->ddev.dev);
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if (error < 0) {
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dev_err(cdd->ddev.dev, "%s pm runtime get: %i\n",
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__func__, error);
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pm_runtime_put_noidle(cdd->ddev.dev);
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return error;
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}
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dma_cookie_init(chan);
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dma_async_tx_descriptor_init(&c->txd, chan);
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c->txd.tx_submit = cppi41_tx_submit;
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if (!c->is_tx)
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cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0);
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pm_runtime_mark_last_busy(cdd->ddev.dev);
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pm_runtime_put_autosuspend(cdd->ddev.dev);
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return 0;
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}
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static void cppi41_dma_free_chan_resources(struct dma_chan *chan)
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{
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struct cppi41_channel *c = to_cpp41_chan(chan);
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struct cppi41_dd *cdd = c->cdd;
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int error;
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error = pm_runtime_get_sync(cdd->ddev.dev);
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if (error < 0) {
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pm_runtime_put_noidle(cdd->ddev.dev);
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return;
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}
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WARN_ON(!list_empty(&cdd->pending));
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pm_runtime_mark_last_busy(cdd->ddev.dev);
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pm_runtime_put_autosuspend(cdd->ddev.dev);
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}
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static enum dma_status cppi41_dma_tx_status(struct dma_chan *chan,
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dma_cookie_t cookie, struct dma_tx_state *txstate)
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{
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struct cppi41_channel *c = to_cpp41_chan(chan);
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enum dma_status ret;
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ret = dma_cookie_status(chan, cookie, txstate);
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dma_set_residue(txstate, c->residue);
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return ret;
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}
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static void push_desc_queue(struct cppi41_channel *c)
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{
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struct cppi41_dd *cdd = c->cdd;
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u32 desc_num;
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u32 desc_phys;
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u32 reg;
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c->residue = 0;
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reg = GCR_CHAN_ENABLE;
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if (!c->is_tx) {
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reg |= GCR_STARV_RETRY;
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reg |= GCR_DESC_TYPE_HOST;
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reg |= c->q_comp_num;
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}
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cppi_writel(reg, c->gcr_reg);
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/*
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* We don't use writel() but __raw_writel() so we have to make sure
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* that the DMA descriptor in coherent memory made to the main memory
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* before starting the dma engine.
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*/
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__iowmb();
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/*
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* DMA transfers can take at least 200ms to complete with USB mass
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* storage connected. To prevent autosuspend timeouts, we must use
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* pm_runtime_get/put() when chan_busy[] is modified. This will get
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* cleared in desc_to_chan() or cppi41_stop_chan() depending on the
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* outcome of the transfer.
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*/
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pm_runtime_get(cdd->ddev.dev);
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desc_phys = lower_32_bits(c->desc_phys);
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desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
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WARN_ON(cdd->chan_busy[desc_num]);
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cdd->chan_busy[desc_num] = c;
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reg = (sizeof(struct cppi41_desc) - 24) / 4;
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reg |= desc_phys;
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cppi_writel(reg, cdd->qmgr_mem + QMGR_QUEUE_D(c->q_num));
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}
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/*
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* Caller must hold cdd->lock to prevent push_desc_queue()
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* getting called out of order. We have both cppi41_dma_issue_pending()
|
|
* and cppi41_runtime_resume() call this function.
|
|
*/
|
|
static void cppi41_run_queue(struct cppi41_dd *cdd)
|
|
{
|
|
struct cppi41_channel *c, *_c;
|
|
|
|
list_for_each_entry_safe(c, _c, &cdd->pending, node) {
|
|
push_desc_queue(c);
|
|
list_del(&c->node);
|
|
}
|
|
}
|
|
|
|
static void cppi41_dma_issue_pending(struct dma_chan *chan)
|
|
{
|
|
struct cppi41_channel *c = to_cpp41_chan(chan);
|
|
struct cppi41_dd *cdd = c->cdd;
|
|
unsigned long flags;
|
|
int error;
|
|
|
|
error = pm_runtime_get(cdd->ddev.dev);
|
|
if ((error != -EINPROGRESS) && error < 0) {
|
|
pm_runtime_put_noidle(cdd->ddev.dev);
|
|
dev_err(cdd->ddev.dev, "Failed to pm_runtime_get: %i\n",
|
|
error);
|
|
|
|
return;
|
|
}
|
|
|
|
spin_lock_irqsave(&cdd->lock, flags);
|
|
list_add_tail(&c->node, &cdd->pending);
|
|
if (!cdd->is_suspended)
|
|
cppi41_run_queue(cdd);
|
|
spin_unlock_irqrestore(&cdd->lock, flags);
|
|
|
|
pm_runtime_mark_last_busy(cdd->ddev.dev);
|
|
pm_runtime_put_autosuspend(cdd->ddev.dev);
|
|
}
|
|
|
|
static u32 get_host_pd0(u32 length)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = DESC_TYPE_HOST << DESC_TYPE;
|
|
reg |= length;
|
|
|
|
return reg;
|
|
}
|
|
|
|
static u32 get_host_pd1(struct cppi41_channel *c)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = 0;
|
|
|
|
return reg;
|
|
}
|
|
|
|
static u32 get_host_pd2(struct cppi41_channel *c)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = DESC_TYPE_USB;
|
|
reg |= c->q_comp_num;
|
|
|
|
return reg;
|
|
}
|
|
|
|
static u32 get_host_pd3(u32 length)
|
|
{
|
|
u32 reg;
|
|
|
|
/* PD3 = packet size */
|
|
reg = length;
|
|
|
|
return reg;
|
|
}
|
|
|
|
static u32 get_host_pd6(u32 length)
|
|
{
|
|
u32 reg;
|
|
|
|
/* PD6 buffer size */
|
|
reg = DESC_PD_COMPLETE;
|
|
reg |= length;
|
|
|
|
return reg;
|
|
}
|
|
|
|
static u32 get_host_pd4_or_7(u32 addr)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = addr;
|
|
|
|
return reg;
|
|
}
|
|
|
|
static u32 get_host_pd5(void)
|
|
{
|
|
u32 reg;
|
|
|
|
reg = 0;
|
|
|
|
return reg;
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *cppi41_dma_prep_slave_sg(
|
|
struct dma_chan *chan, struct scatterlist *sgl, unsigned sg_len,
|
|
enum dma_transfer_direction dir, unsigned long tx_flags, void *context)
|
|
{
|
|
struct cppi41_channel *c = to_cpp41_chan(chan);
|
|
struct cppi41_desc *d;
|
|
struct scatterlist *sg;
|
|
unsigned int i;
|
|
|
|
d = c->desc;
|
|
for_each_sg(sgl, sg, sg_len, i) {
|
|
u32 addr;
|
|
u32 len;
|
|
|
|
/* We need to use more than one desc once musb supports sg */
|
|
addr = lower_32_bits(sg_dma_address(sg));
|
|
len = sg_dma_len(sg);
|
|
|
|
d->pd0 = get_host_pd0(len);
|
|
d->pd1 = get_host_pd1(c);
|
|
d->pd2 = get_host_pd2(c);
|
|
d->pd3 = get_host_pd3(len);
|
|
d->pd4 = get_host_pd4_or_7(addr);
|
|
d->pd5 = get_host_pd5();
|
|
d->pd6 = get_host_pd6(len);
|
|
d->pd7 = get_host_pd4_or_7(addr);
|
|
|
|
d++;
|
|
}
|
|
|
|
return &c->txd;
|
|
}
|
|
|
|
static void cppi41_compute_td_desc(struct cppi41_desc *d)
|
|
{
|
|
d->pd0 = DESC_TYPE_TEARD << DESC_TYPE;
|
|
}
|
|
|
|
static int cppi41_tear_down_chan(struct cppi41_channel *c)
|
|
{
|
|
struct dmaengine_result abort_result;
|
|
struct cppi41_dd *cdd = c->cdd;
|
|
struct cppi41_desc *td;
|
|
u32 reg;
|
|
u32 desc_phys;
|
|
u32 td_desc_phys;
|
|
|
|
td = cdd->cd;
|
|
td += cdd->first_td_desc;
|
|
|
|
td_desc_phys = cdd->descs_phys;
|
|
td_desc_phys += cdd->first_td_desc * sizeof(struct cppi41_desc);
|
|
|
|
if (!c->td_queued) {
|
|
cppi41_compute_td_desc(td);
|
|
__iowmb();
|
|
|
|
reg = (sizeof(struct cppi41_desc) - 24) / 4;
|
|
reg |= td_desc_phys;
|
|
cppi_writel(reg, cdd->qmgr_mem +
|
|
QMGR_QUEUE_D(cdd->td_queue.submit));
|
|
|
|
reg = GCR_CHAN_ENABLE;
|
|
if (!c->is_tx) {
|
|
reg |= GCR_STARV_RETRY;
|
|
reg |= GCR_DESC_TYPE_HOST;
|
|
reg |= cdd->td_queue.complete;
|
|
}
|
|
reg |= GCR_TEARDOWN;
|
|
cppi_writel(reg, c->gcr_reg);
|
|
c->td_queued = 1;
|
|
c->td_retry = 500;
|
|
}
|
|
|
|
if (!c->td_seen || !c->td_desc_seen) {
|
|
|
|
desc_phys = cppi41_pop_desc(cdd, cdd->td_queue.complete);
|
|
if (!desc_phys && c->is_tx)
|
|
desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
|
|
|
|
if (desc_phys == c->desc_phys) {
|
|
c->td_desc_seen = 1;
|
|
|
|
} else if (desc_phys == td_desc_phys) {
|
|
u32 pd0;
|
|
|
|
__iormb();
|
|
pd0 = td->pd0;
|
|
WARN_ON((pd0 >> DESC_TYPE) != DESC_TYPE_TEARD);
|
|
WARN_ON(!c->is_tx && !(pd0 & TD_DESC_IS_RX));
|
|
WARN_ON((pd0 & 0x1f) != c->port_num);
|
|
c->td_seen = 1;
|
|
} else if (desc_phys) {
|
|
WARN_ON_ONCE(1);
|
|
}
|
|
}
|
|
c->td_retry--;
|
|
/*
|
|
* If the TX descriptor / channel is in use, the caller needs to poke
|
|
* his TD bit multiple times. After that he hardware releases the
|
|
* transfer descriptor followed by TD descriptor. Waiting seems not to
|
|
* cause any difference.
|
|
* RX seems to be thrown out right away. However once the TearDown
|
|
* descriptor gets through we are done. If we have seens the transfer
|
|
* descriptor before the TD we fetch it from enqueue, it has to be
|
|
* there waiting for us.
|
|
*/
|
|
if (!c->td_seen && c->td_retry) {
|
|
udelay(1);
|
|
return -EAGAIN;
|
|
}
|
|
WARN_ON(!c->td_retry);
|
|
|
|
if (!c->td_desc_seen) {
|
|
desc_phys = cppi41_pop_desc(cdd, c->q_num);
|
|
if (!desc_phys)
|
|
desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
|
|
WARN_ON(!desc_phys);
|
|
}
|
|
|
|
c->td_queued = 0;
|
|
c->td_seen = 0;
|
|
c->td_desc_seen = 0;
|
|
cppi_writel(0, c->gcr_reg);
|
|
|
|
/* Invoke the callback to do the necessary clean-up */
|
|
abort_result.result = DMA_TRANS_ABORTED;
|
|
dma_cookie_complete(&c->txd);
|
|
dmaengine_desc_get_callback_invoke(&c->txd, &abort_result);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cppi41_stop_chan(struct dma_chan *chan)
|
|
{
|
|
struct cppi41_channel *c = to_cpp41_chan(chan);
|
|
struct cppi41_dd *cdd = c->cdd;
|
|
u32 desc_num;
|
|
u32 desc_phys;
|
|
int ret;
|
|
|
|
desc_phys = lower_32_bits(c->desc_phys);
|
|
desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
|
|
if (!cdd->chan_busy[desc_num])
|
|
return 0;
|
|
|
|
ret = cppi41_tear_down_chan(c);
|
|
if (ret)
|
|
return ret;
|
|
|
|
WARN_ON(!cdd->chan_busy[desc_num]);
|
|
cdd->chan_busy[desc_num] = NULL;
|
|
|
|
/* Usecount for chan_busy[], paired with push_desc_queue() */
|
|
pm_runtime_put(cdd->ddev.dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cppi41_add_chans(struct device *dev, struct cppi41_dd *cdd)
|
|
{
|
|
struct cppi41_channel *cchan, *chans;
|
|
int i;
|
|
u32 n_chans = cdd->n_chans;
|
|
|
|
/*
|
|
* The channels can only be used as TX or as RX. So we add twice
|
|
* that much dma channels because USB can only do RX or TX.
|
|
*/
|
|
n_chans *= 2;
|
|
|
|
chans = devm_kcalloc(dev, n_chans, sizeof(*chans), GFP_KERNEL);
|
|
if (!chans)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < n_chans; i++) {
|
|
cchan = &chans[i];
|
|
|
|
cchan->cdd = cdd;
|
|
if (i & 1) {
|
|
cchan->gcr_reg = cdd->ctrl_mem + DMA_TXGCR(i >> 1);
|
|
cchan->is_tx = 1;
|
|
} else {
|
|
cchan->gcr_reg = cdd->ctrl_mem + DMA_RXGCR(i >> 1);
|
|
cchan->is_tx = 0;
|
|
}
|
|
cchan->port_num = i >> 1;
|
|
cchan->desc = &cdd->cd[i];
|
|
cchan->desc_phys = cdd->descs_phys;
|
|
cchan->desc_phys += i * sizeof(struct cppi41_desc);
|
|
cchan->chan.device = &cdd->ddev;
|
|
list_add_tail(&cchan->chan.device_node, &cdd->ddev.channels);
|
|
}
|
|
cdd->first_td_desc = n_chans;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void purge_descs(struct device *dev, struct cppi41_dd *cdd)
|
|
{
|
|
unsigned int mem_decs;
|
|
int i;
|
|
|
|
mem_decs = ALLOC_DECS_NUM * sizeof(struct cppi41_desc);
|
|
|
|
for (i = 0; i < DESCS_AREAS; i++) {
|
|
|
|
cppi_writel(0, cdd->qmgr_mem + QMGR_MEMBASE(i));
|
|
cppi_writel(0, cdd->qmgr_mem + QMGR_MEMCTRL(i));
|
|
|
|
dma_free_coherent(dev, mem_decs, cdd->cd,
|
|
cdd->descs_phys);
|
|
}
|
|
}
|
|
|
|
static void disable_sched(struct cppi41_dd *cdd)
|
|
{
|
|
cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
|
|
}
|
|
|
|
static void deinit_cppi41(struct device *dev, struct cppi41_dd *cdd)
|
|
{
|
|
disable_sched(cdd);
|
|
|
|
purge_descs(dev, cdd);
|
|
|
|
cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
|
|
cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM0_BASE);
|
|
dma_free_coherent(dev, QMGR_SCRATCH_SIZE, cdd->qmgr_scratch,
|
|
cdd->scratch_phys);
|
|
}
|
|
|
|
static int init_descs(struct device *dev, struct cppi41_dd *cdd)
|
|
{
|
|
unsigned int desc_size;
|
|
unsigned int mem_decs;
|
|
int i;
|
|
u32 reg;
|
|
u32 idx;
|
|
|
|
BUILD_BUG_ON(sizeof(struct cppi41_desc) &
|
|
(sizeof(struct cppi41_desc) - 1));
|
|
BUILD_BUG_ON(sizeof(struct cppi41_desc) < 32);
|
|
BUILD_BUG_ON(ALLOC_DECS_NUM < 32);
|
|
|
|
desc_size = sizeof(struct cppi41_desc);
|
|
mem_decs = ALLOC_DECS_NUM * desc_size;
|
|
|
|
idx = 0;
|
|
for (i = 0; i < DESCS_AREAS; i++) {
|
|
|
|
reg = idx << QMGR_MEMCTRL_IDX_SH;
|
|
reg |= (ilog2(desc_size) - 5) << QMGR_MEMCTRL_DESC_SH;
|
|
reg |= ilog2(ALLOC_DECS_NUM) - 5;
|
|
|
|
BUILD_BUG_ON(DESCS_AREAS != 1);
|
|
cdd->cd = dma_alloc_coherent(dev, mem_decs,
|
|
&cdd->descs_phys, GFP_KERNEL);
|
|
if (!cdd->cd)
|
|
return -ENOMEM;
|
|
|
|
cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
|
|
cppi_writel(reg, cdd->qmgr_mem + QMGR_MEMCTRL(i));
|
|
|
|
idx += ALLOC_DECS_NUM;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void init_sched(struct cppi41_dd *cdd)
|
|
{
|
|
unsigned ch;
|
|
unsigned word;
|
|
u32 reg;
|
|
|
|
word = 0;
|
|
cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
|
|
for (ch = 0; ch < cdd->n_chans; ch += 2) {
|
|
|
|
reg = SCHED_ENTRY0_CHAN(ch);
|
|
reg |= SCHED_ENTRY1_CHAN(ch) | SCHED_ENTRY1_IS_RX;
|
|
|
|
reg |= SCHED_ENTRY2_CHAN(ch + 1);
|
|
reg |= SCHED_ENTRY3_CHAN(ch + 1) | SCHED_ENTRY3_IS_RX;
|
|
cppi_writel(reg, cdd->sched_mem + DMA_SCHED_WORD(word));
|
|
word++;
|
|
}
|
|
reg = cdd->n_chans * 2 - 1;
|
|
reg |= DMA_SCHED_CTRL_EN;
|
|
cppi_writel(reg, cdd->sched_mem + DMA_SCHED_CTRL);
|
|
}
|
|
|
|
static int init_cppi41(struct device *dev, struct cppi41_dd *cdd)
|
|
{
|
|
int ret;
|
|
|
|
BUILD_BUG_ON(QMGR_SCRATCH_SIZE > ((1 << 14) - 1));
|
|
cdd->qmgr_scratch = dma_alloc_coherent(dev, QMGR_SCRATCH_SIZE,
|
|
&cdd->scratch_phys, GFP_KERNEL);
|
|
if (!cdd->qmgr_scratch)
|
|
return -ENOMEM;
|
|
|
|
cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
|
|
cppi_writel(TOTAL_DESCS_NUM, cdd->qmgr_mem + QMGR_LRAM_SIZE);
|
|
cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
|
|
|
|
ret = init_descs(dev, cdd);
|
|
if (ret)
|
|
goto err_td;
|
|
|
|
cppi_writel(cdd->td_queue.submit, cdd->ctrl_mem + DMA_TDFDQ);
|
|
init_sched(cdd);
|
|
|
|
return 0;
|
|
err_td:
|
|
deinit_cppi41(dev, cdd);
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver cpp41_dma_driver;
|
|
/*
|
|
* The param format is:
|
|
* X Y
|
|
* X: Port
|
|
* Y: 0 = RX else TX
|
|
*/
|
|
#define INFO_PORT 0
|
|
#define INFO_IS_TX 1
|
|
|
|
static bool cpp41_dma_filter_fn(struct dma_chan *chan, void *param)
|
|
{
|
|
struct cppi41_channel *cchan;
|
|
struct cppi41_dd *cdd;
|
|
const struct chan_queues *queues;
|
|
u32 *num = param;
|
|
|
|
if (chan->device->dev->driver != &cpp41_dma_driver.driver)
|
|
return false;
|
|
|
|
cchan = to_cpp41_chan(chan);
|
|
|
|
if (cchan->port_num != num[INFO_PORT])
|
|
return false;
|
|
|
|
if (cchan->is_tx && !num[INFO_IS_TX])
|
|
return false;
|
|
cdd = cchan->cdd;
|
|
if (cchan->is_tx)
|
|
queues = cdd->queues_tx;
|
|
else
|
|
queues = cdd->queues_rx;
|
|
|
|
BUILD_BUG_ON(ARRAY_SIZE(am335x_usb_queues_rx) !=
|
|
ARRAY_SIZE(am335x_usb_queues_tx));
|
|
if (WARN_ON(cchan->port_num >= ARRAY_SIZE(am335x_usb_queues_rx)))
|
|
return false;
|
|
|
|
cchan->q_num = queues[cchan->port_num].submit;
|
|
cchan->q_comp_num = queues[cchan->port_num].complete;
|
|
return true;
|
|
}
|
|
|
|
static struct of_dma_filter_info cpp41_dma_info = {
|
|
.filter_fn = cpp41_dma_filter_fn,
|
|
};
|
|
|
|
static struct dma_chan *cppi41_dma_xlate(struct of_phandle_args *dma_spec,
|
|
struct of_dma *ofdma)
|
|
{
|
|
int count = dma_spec->args_count;
|
|
struct of_dma_filter_info *info = ofdma->of_dma_data;
|
|
|
|
if (!info || !info->filter_fn)
|
|
return NULL;
|
|
|
|
if (count != 2)
|
|
return NULL;
|
|
|
|
return dma_request_channel(info->dma_cap, info->filter_fn,
|
|
&dma_spec->args[0]);
|
|
}
|
|
|
|
static const struct cppi_glue_infos am335x_usb_infos = {
|
|
.queues_rx = am335x_usb_queues_rx,
|
|
.queues_tx = am335x_usb_queues_tx,
|
|
.td_queue = { .submit = 31, .complete = 0 },
|
|
.first_completion_queue = 93,
|
|
.qmgr_num_pend = 5,
|
|
};
|
|
|
|
static const struct cppi_glue_infos da8xx_usb_infos = {
|
|
.queues_rx = da8xx_usb_queues_rx,
|
|
.queues_tx = da8xx_usb_queues_tx,
|
|
.td_queue = { .submit = 31, .complete = 0 },
|
|
.first_completion_queue = 24,
|
|
.qmgr_num_pend = 2,
|
|
};
|
|
|
|
static const struct of_device_id cppi41_dma_ids[] = {
|
|
{ .compatible = "ti,am3359-cppi41", .data = &am335x_usb_infos},
|
|
{ .compatible = "ti,da830-cppi41", .data = &da8xx_usb_infos},
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, cppi41_dma_ids);
|
|
|
|
static const struct cppi_glue_infos *get_glue_info(struct device *dev)
|
|
{
|
|
const struct of_device_id *of_id;
|
|
|
|
of_id = of_match_node(cppi41_dma_ids, dev->of_node);
|
|
if (!of_id)
|
|
return NULL;
|
|
return of_id->data;
|
|
}
|
|
|
|
#define CPPI41_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
|
|
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
|
|
BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
|
|
BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
|
|
|
|
static int cppi41_dma_probe(struct platform_device *pdev)
|
|
{
|
|
struct cppi41_dd *cdd;
|
|
struct device *dev = &pdev->dev;
|
|
const struct cppi_glue_infos *glue_info;
|
|
struct resource *mem;
|
|
int index;
|
|
int irq;
|
|
int ret;
|
|
|
|
glue_info = get_glue_info(dev);
|
|
if (!glue_info)
|
|
return -EINVAL;
|
|
|
|
cdd = devm_kzalloc(&pdev->dev, sizeof(*cdd), GFP_KERNEL);
|
|
if (!cdd)
|
|
return -ENOMEM;
|
|
|
|
dma_cap_set(DMA_SLAVE, cdd->ddev.cap_mask);
|
|
cdd->ddev.device_alloc_chan_resources = cppi41_dma_alloc_chan_resources;
|
|
cdd->ddev.device_free_chan_resources = cppi41_dma_free_chan_resources;
|
|
cdd->ddev.device_tx_status = cppi41_dma_tx_status;
|
|
cdd->ddev.device_issue_pending = cppi41_dma_issue_pending;
|
|
cdd->ddev.device_prep_slave_sg = cppi41_dma_prep_slave_sg;
|
|
cdd->ddev.device_terminate_all = cppi41_stop_chan;
|
|
cdd->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
|
|
cdd->ddev.src_addr_widths = CPPI41_DMA_BUSWIDTHS;
|
|
cdd->ddev.dst_addr_widths = CPPI41_DMA_BUSWIDTHS;
|
|
cdd->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
|
|
cdd->ddev.dev = dev;
|
|
INIT_LIST_HEAD(&cdd->ddev.channels);
|
|
cpp41_dma_info.dma_cap = cdd->ddev.cap_mask;
|
|
|
|
index = of_property_match_string(dev->of_node,
|
|
"reg-names", "controller");
|
|
if (index < 0)
|
|
return index;
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, index);
|
|
cdd->ctrl_mem = devm_ioremap_resource(dev, mem);
|
|
if (IS_ERR(cdd->ctrl_mem))
|
|
return PTR_ERR(cdd->ctrl_mem);
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, index + 1);
|
|
cdd->sched_mem = devm_ioremap_resource(dev, mem);
|
|
if (IS_ERR(cdd->sched_mem))
|
|
return PTR_ERR(cdd->sched_mem);
|
|
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, index + 2);
|
|
cdd->qmgr_mem = devm_ioremap_resource(dev, mem);
|
|
if (IS_ERR(cdd->qmgr_mem))
|
|
return PTR_ERR(cdd->qmgr_mem);
|
|
|
|
spin_lock_init(&cdd->lock);
|
|
INIT_LIST_HEAD(&cdd->pending);
|
|
|
|
platform_set_drvdata(pdev, cdd);
|
|
|
|
pm_runtime_enable(dev);
|
|
pm_runtime_set_autosuspend_delay(dev, 100);
|
|
pm_runtime_use_autosuspend(dev);
|
|
ret = pm_runtime_get_sync(dev);
|
|
if (ret < 0)
|
|
goto err_get_sync;
|
|
|
|
cdd->queues_rx = glue_info->queues_rx;
|
|
cdd->queues_tx = glue_info->queues_tx;
|
|
cdd->td_queue = glue_info->td_queue;
|
|
cdd->qmgr_num_pend = glue_info->qmgr_num_pend;
|
|
cdd->first_completion_queue = glue_info->first_completion_queue;
|
|
|
|
ret = of_property_read_u32(dev->of_node,
|
|
"#dma-channels", &cdd->n_chans);
|
|
if (ret)
|
|
goto err_get_n_chans;
|
|
|
|
ret = init_cppi41(dev, cdd);
|
|
if (ret)
|
|
goto err_init_cppi;
|
|
|
|
ret = cppi41_add_chans(dev, cdd);
|
|
if (ret)
|
|
goto err_chans;
|
|
|
|
irq = irq_of_parse_and_map(dev->of_node, 0);
|
|
if (!irq) {
|
|
ret = -EINVAL;
|
|
goto err_chans;
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, cppi41_irq, IRQF_SHARED,
|
|
dev_name(dev), cdd);
|
|
if (ret)
|
|
goto err_chans;
|
|
cdd->irq = irq;
|
|
|
|
ret = dma_async_device_register(&cdd->ddev);
|
|
if (ret)
|
|
goto err_chans;
|
|
|
|
ret = of_dma_controller_register(dev->of_node,
|
|
cppi41_dma_xlate, &cpp41_dma_info);
|
|
if (ret)
|
|
goto err_of;
|
|
|
|
pm_runtime_mark_last_busy(dev);
|
|
pm_runtime_put_autosuspend(dev);
|
|
|
|
return 0;
|
|
err_of:
|
|
dma_async_device_unregister(&cdd->ddev);
|
|
err_chans:
|
|
deinit_cppi41(dev, cdd);
|
|
err_init_cppi:
|
|
pm_runtime_dont_use_autosuspend(dev);
|
|
err_get_n_chans:
|
|
err_get_sync:
|
|
pm_runtime_put_sync(dev);
|
|
pm_runtime_disable(dev);
|
|
return ret;
|
|
}
|
|
|
|
static int cppi41_dma_remove(struct platform_device *pdev)
|
|
{
|
|
struct cppi41_dd *cdd = platform_get_drvdata(pdev);
|
|
int error;
|
|
|
|
error = pm_runtime_get_sync(&pdev->dev);
|
|
if (error < 0)
|
|
dev_err(&pdev->dev, "%s could not pm_runtime_get: %i\n",
|
|
__func__, error);
|
|
of_dma_controller_free(pdev->dev.of_node);
|
|
dma_async_device_unregister(&cdd->ddev);
|
|
|
|
devm_free_irq(&pdev->dev, cdd->irq, cdd);
|
|
deinit_cppi41(&pdev->dev, cdd);
|
|
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused cppi41_suspend(struct device *dev)
|
|
{
|
|
struct cppi41_dd *cdd = dev_get_drvdata(dev);
|
|
|
|
cdd->dma_tdfdq = cppi_readl(cdd->ctrl_mem + DMA_TDFDQ);
|
|
disable_sched(cdd);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused cppi41_resume(struct device *dev)
|
|
{
|
|
struct cppi41_dd *cdd = dev_get_drvdata(dev);
|
|
struct cppi41_channel *c;
|
|
int i;
|
|
|
|
for (i = 0; i < DESCS_AREAS; i++)
|
|
cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
|
|
|
|
list_for_each_entry(c, &cdd->ddev.channels, chan.device_node)
|
|
if (!c->is_tx)
|
|
cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0);
|
|
|
|
init_sched(cdd);
|
|
|
|
cppi_writel(cdd->dma_tdfdq, cdd->ctrl_mem + DMA_TDFDQ);
|
|
cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
|
|
cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
|
|
cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused cppi41_runtime_suspend(struct device *dev)
|
|
{
|
|
struct cppi41_dd *cdd = dev_get_drvdata(dev);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&cdd->lock, flags);
|
|
cdd->is_suspended = true;
|
|
WARN_ON(!list_empty(&cdd->pending));
|
|
spin_unlock_irqrestore(&cdd->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __maybe_unused cppi41_runtime_resume(struct device *dev)
|
|
{
|
|
struct cppi41_dd *cdd = dev_get_drvdata(dev);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&cdd->lock, flags);
|
|
cdd->is_suspended = false;
|
|
cppi41_run_queue(cdd);
|
|
spin_unlock_irqrestore(&cdd->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops cppi41_pm_ops = {
|
|
SET_LATE_SYSTEM_SLEEP_PM_OPS(cppi41_suspend, cppi41_resume)
|
|
SET_RUNTIME_PM_OPS(cppi41_runtime_suspend,
|
|
cppi41_runtime_resume,
|
|
NULL)
|
|
};
|
|
|
|
static struct platform_driver cpp41_dma_driver = {
|
|
.probe = cppi41_dma_probe,
|
|
.remove = cppi41_dma_remove,
|
|
.driver = {
|
|
.name = "cppi41-dma-engine",
|
|
.pm = &cppi41_pm_ops,
|
|
.of_match_table = of_match_ptr(cppi41_dma_ids),
|
|
},
|
|
};
|
|
|
|
module_platform_driver(cpp41_dma_driver);
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Sebastian Andrzej Siewior <bigeasy@linutronix.de>");
|