486 lines
12 KiB
C
486 lines
12 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Copyright 2012 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/can/platform/flexcan.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/micrel_phy.h>
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#include <linux/mxsfb.h>
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#include <linux/of_platform.h>
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#include <linux/phy.h>
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#include <linux/pinctrl/consumer.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include <mach/common.h>
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#include <mach/digctl.h>
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#include <mach/mxs.h>
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static struct fb_videomode mx23evk_video_modes[] = {
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{
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.name = "Samsung-LMS430HF02",
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.refresh = 60,
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.xres = 480,
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.yres = 272,
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.pixclock = 108096, /* picosecond (9.2 MHz) */
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.left_margin = 15,
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.right_margin = 8,
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.upper_margin = 12,
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.lower_margin = 4,
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.hsync_len = 1,
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.vsync_len = 1,
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},
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};
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static struct fb_videomode mx28evk_video_modes[] = {
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{
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.name = "Seiko-43WVF1G",
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.refresh = 60,
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.xres = 800,
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.yres = 480,
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.pixclock = 29851, /* picosecond (33.5 MHz) */
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.left_margin = 89,
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.right_margin = 164,
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.upper_margin = 23,
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.lower_margin = 10,
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.hsync_len = 10,
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.vsync_len = 10,
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},
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};
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static struct fb_videomode m28evk_video_modes[] = {
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{
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.name = "Ampire AM-800480R2TMQW-T01H",
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.refresh = 60,
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.xres = 800,
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.yres = 480,
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.pixclock = 30066, /* picosecond (33.26 MHz) */
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.left_margin = 0,
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.right_margin = 256,
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.upper_margin = 0,
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.lower_margin = 45,
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.hsync_len = 1,
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.vsync_len = 1,
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},
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};
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static struct fb_videomode apx4devkit_video_modes[] = {
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{
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.name = "HannStar PJ70112A",
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.refresh = 60,
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.xres = 800,
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.yres = 480,
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.pixclock = 33333, /* picosecond (30.00 MHz) */
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.left_margin = 88,
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.right_margin = 40,
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.upper_margin = 32,
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.lower_margin = 13,
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.hsync_len = 48,
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.vsync_len = 3,
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.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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},
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};
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static struct fb_videomode apf28dev_video_modes[] = {
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{
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.name = "LW700",
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.refresh = 60,
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.xres = 800,
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.yres = 480,
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.pixclock = 30303, /* picosecond */
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.left_margin = 96,
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.right_margin = 96, /* at least 3 & 1 */
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.upper_margin = 0x14,
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.lower_margin = 0x15,
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.hsync_len = 64,
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.vsync_len = 4,
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.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
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},
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};
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static struct fb_videomode cfa10049_video_modes[] = {
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{
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.name = "Himax HX8357-B",
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.refresh = 60,
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.xres = 320,
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.yres = 480,
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.pixclock = 108506, /* picosecond (9.216 MHz) */
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.left_margin = 2,
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.right_margin = 2,
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.upper_margin = 2,
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.lower_margin = 2,
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.hsync_len = 15,
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.vsync_len = 15,
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},
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};
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static struct mxsfb_platform_data mxsfb_pdata __initdata;
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/*
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* MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
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*/
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#define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13)
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static int flexcan0_en, flexcan1_en;
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static void mx28evk_flexcan_switch(void)
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{
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if (flexcan0_en || flexcan1_en)
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gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
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else
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gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
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}
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static void mx28evk_flexcan0_switch(int enable)
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{
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flexcan0_en = enable;
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mx28evk_flexcan_switch();
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}
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static void mx28evk_flexcan1_switch(int enable)
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{
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flexcan1_en = enable;
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mx28evk_flexcan_switch();
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}
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static struct flexcan_platform_data flexcan_pdata[2];
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static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata),
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OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata),
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OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]),
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OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]),
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{ /* sentinel */ }
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};
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static void __init imx23_timer_init(void)
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{
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mx23_clocks_init();
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}
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static void __init imx28_timer_init(void)
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{
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mx28_clocks_init();
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}
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enum mac_oui {
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OUI_FSL,
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OUI_DENX,
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OUI_CRYSTALFONTZ,
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};
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static void __init update_fec_mac_prop(enum mac_oui oui)
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{
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struct device_node *np, *from = NULL;
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struct property *newmac;
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const u32 *ocotp = mxs_get_ocotp();
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u8 *macaddr;
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u32 val;
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int i;
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for (i = 0; i < 2; i++) {
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np = of_find_compatible_node(from, NULL, "fsl,imx28-fec");
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if (!np)
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return;
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from = np;
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if (of_get_property(np, "local-mac-address", NULL))
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continue;
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newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
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if (!newmac)
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return;
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newmac->value = newmac + 1;
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newmac->length = 6;
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newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
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if (!newmac->name) {
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kfree(newmac);
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return;
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}
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/*
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* OCOTP only stores the last 4 octets for each mac address,
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* so hard-code OUI here.
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*/
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macaddr = newmac->value;
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switch (oui) {
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case OUI_FSL:
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macaddr[0] = 0x00;
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macaddr[1] = 0x04;
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macaddr[2] = 0x9f;
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break;
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case OUI_DENX:
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macaddr[0] = 0xc0;
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macaddr[1] = 0xe5;
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macaddr[2] = 0x4e;
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break;
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case OUI_CRYSTALFONTZ:
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macaddr[0] = 0x58;
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macaddr[1] = 0xb9;
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macaddr[2] = 0xe1;
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break;
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}
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val = ocotp[i];
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macaddr[3] = (val >> 16) & 0xff;
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macaddr[4] = (val >> 8) & 0xff;
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macaddr[5] = (val >> 0) & 0xff;
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of_update_property(np, newmac);
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}
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}
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static void __init imx23_evk_init(void)
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{
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mxsfb_pdata.mode_list = mx23evk_video_modes;
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mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes);
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mxsfb_pdata.default_bpp = 32;
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mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
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mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
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MXSFB_SYNC_DOTCLK_FAILING_ACT;
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}
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static inline void enable_clk_enet_out(void)
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{
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struct clk *clk = clk_get_sys("enet_out", NULL);
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if (!IS_ERR(clk))
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clk_prepare_enable(clk);
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}
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static void __init imx28_evk_init(void)
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{
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enable_clk_enet_out();
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update_fec_mac_prop(OUI_FSL);
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mxsfb_pdata.mode_list = mx28evk_video_modes;
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mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes);
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mxsfb_pdata.default_bpp = 32;
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mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
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mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
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MXSFB_SYNC_DOTCLK_FAILING_ACT;
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mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
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}
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static void __init imx28_evk_post_init(void)
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{
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if (!gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
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"flexcan-switch")) {
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flexcan_pdata[0].transceiver_switch = mx28evk_flexcan0_switch;
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flexcan_pdata[1].transceiver_switch = mx28evk_flexcan1_switch;
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}
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}
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static void __init m28evk_init(void)
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{
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mxsfb_pdata.mode_list = m28evk_video_modes;
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mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes);
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mxsfb_pdata.default_bpp = 16;
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mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
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mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
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}
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static void __init sc_sps1_init(void)
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{
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enable_clk_enet_out();
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}
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static int apx4devkit_phy_fixup(struct phy_device *phy)
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{
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phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
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return 0;
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}
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static void __init apx4devkit_init(void)
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{
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enable_clk_enet_out();
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if (IS_BUILTIN(CONFIG_PHYLIB))
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phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK,
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apx4devkit_phy_fixup);
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mxsfb_pdata.mode_list = apx4devkit_video_modes;
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mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes);
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mxsfb_pdata.default_bpp = 32;
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mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
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mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
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MXSFB_SYNC_DOTCLK_FAILING_ACT;
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}
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#define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0)
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#define ENET0_MDIO__GPIO_4_1 MXS_GPIO_NR(4, 1)
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#define ENET0_RX_EN__GPIO_4_2 MXS_GPIO_NR(4, 2)
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#define ENET0_RXD0__GPIO_4_3 MXS_GPIO_NR(4, 3)
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#define ENET0_RXD1__GPIO_4_4 MXS_GPIO_NR(4, 4)
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#define ENET0_TX_EN__GPIO_4_6 MXS_GPIO_NR(4, 6)
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#define ENET0_TXD0__GPIO_4_7 MXS_GPIO_NR(4, 7)
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#define ENET0_TXD1__GPIO_4_8 MXS_GPIO_NR(4, 8)
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#define ENET_CLK__GPIO_4_16 MXS_GPIO_NR(4, 16)
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#define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29)
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#define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
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#define TX28_FEC_nINT MXS_GPIO_NR(4, 5)
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static const struct gpio tx28_gpios[] __initconst = {
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{ ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" },
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{ ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" },
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{ ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" },
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{ ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" },
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{ ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" },
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{ ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" },
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{ ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" },
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{ ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" },
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{ ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" },
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{ TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
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{ TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" },
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{ TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" },
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};
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static void __init tx28_post_init(void)
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{
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struct device_node *np;
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struct platform_device *pdev;
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struct pinctrl *pctl;
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int ret;
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enable_clk_enet_out();
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np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec");
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pdev = of_find_device_by_node(np);
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if (!pdev) {
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pr_err("%s: failed to find fec device\n", __func__);
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return;
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}
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pctl = pinctrl_get_select(&pdev->dev, "gpio_mode");
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if (IS_ERR(pctl)) {
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pr_err("%s: failed to get pinctrl state\n", __func__);
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return;
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}
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ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
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if (ret) {
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pr_err("%s: failed to request gpios: %d\n", __func__, ret);
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return;
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}
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/* Power up fec phy */
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gpio_set_value(TX28_FEC_PHY_POWER, 1);
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msleep(26); /* 25ms according to data sheet */
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/* Mode strap pins */
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gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1);
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gpio_set_value(ENET0_RXD0__GPIO_4_3, 1);
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gpio_set_value(ENET0_RXD1__GPIO_4_4, 1);
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udelay(100); /* minimum assertion time for nRST */
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/* Deasserting FEC PHY RESET */
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gpio_set_value(TX28_FEC_PHY_RESET, 1);
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pinctrl_put(pctl);
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}
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static void __init cfa10049_init(void)
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{
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enable_clk_enet_out();
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update_fec_mac_prop(OUI_CRYSTALFONTZ);
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mxsfb_pdata.mode_list = cfa10049_video_modes;
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mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes);
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mxsfb_pdata.default_bpp = 32;
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mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
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mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT;
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}
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static void __init cfa10037_init(void)
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{
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enable_clk_enet_out();
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update_fec_mac_prop(OUI_CRYSTALFONTZ);
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}
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static void __init apf28_init(void)
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{
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enable_clk_enet_out();
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mxsfb_pdata.mode_list = apf28dev_video_modes;
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mxsfb_pdata.mode_count = ARRAY_SIZE(apf28dev_video_modes);
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mxsfb_pdata.default_bpp = 16;
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mxsfb_pdata.ld_intf_width = STMLCDIF_16BIT;
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mxsfb_pdata.sync = MXSFB_SYNC_DATA_ENABLE_HIGH_ACT |
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MXSFB_SYNC_DOTCLK_FAILING_ACT;
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}
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static void __init mxs_machine_init(void)
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{
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if (of_machine_is_compatible("fsl,imx28-evk"))
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imx28_evk_init();
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else if (of_machine_is_compatible("fsl,imx23-evk"))
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imx23_evk_init();
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else if (of_machine_is_compatible("denx,m28evk"))
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m28evk_init();
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else if (of_machine_is_compatible("bluegiga,apx4devkit"))
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apx4devkit_init();
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else if (of_machine_is_compatible("crystalfontz,cfa10037"))
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cfa10037_init();
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else if (of_machine_is_compatible("crystalfontz,cfa10049"))
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cfa10049_init();
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else if (of_machine_is_compatible("armadeus,imx28-apf28"))
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apf28_init();
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else if (of_machine_is_compatible("schulercontrol,imx28-sps1"))
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sc_sps1_init();
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of_platform_populate(NULL, of_default_bus_match_table,
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mxs_auxdata_lookup, NULL);
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if (of_machine_is_compatible("karo,tx28"))
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tx28_post_init();
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if (of_machine_is_compatible("fsl,imx28-evk"))
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imx28_evk_post_init();
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}
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static const char *imx23_dt_compat[] __initdata = {
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"fsl,imx23",
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NULL,
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};
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static const char *imx28_dt_compat[] __initdata = {
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"fsl,imx28",
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NULL,
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};
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DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)")
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.map_io = mx23_map_io,
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.init_irq = icoll_init_irq,
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.handle_irq = icoll_handle_irq,
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.init_time = imx23_timer_init,
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.init_machine = mxs_machine_init,
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.dt_compat = imx23_dt_compat,
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.restart = mxs_restart,
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MACHINE_END
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|
|
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DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
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.map_io = mx28_map_io,
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|
.init_irq = icoll_init_irq,
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|
.handle_irq = icoll_handle_irq,
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|
.init_time = imx28_timer_init,
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|
.init_machine = mxs_machine_init,
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|
.dt_compat = imx28_dt_compat,
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|
.restart = mxs_restart,
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|
MACHINE_END
|