566 lines
14 KiB
C
566 lines
14 KiB
C
/*
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* linux/arch/arm/mach-integrator/integrator_cp.c
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*
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* Copyright (C) 2003 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/string.h>
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#include <linux/device.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/kmi.h>
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#include <linux/amba/clcd.h>
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#include <linux/amba/mmci.h>
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#include <linux/io.h>
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#include <linux/irqchip/versatile-fpga.h>
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#include <linux/gfp.h>
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#include <linux/mtd/physmap.h>
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#include <linux/platform_data/clk-integrator.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/sys_soc.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/hardware/arm_timer.h>
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#include <asm/hardware/icst.h>
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#include <mach/cm.h>
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#include <mach/lm.h>
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#include <mach/irqs.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/hardware/timer-sp.h>
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#include <plat/clcd.h>
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#include <plat/sched_clock.h>
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#include "common.h"
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/* Base address to the CP controller */
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static void __iomem *intcp_con_base;
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#define INTCP_PA_FLASH_BASE 0x24000000
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#define INTCP_PA_CLCD_BASE 0xc0000000
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#define INTCP_FLASHPROG 0x04
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#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
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#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
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/*
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* Logical Physical
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* f1000000 10000000 Core module registers
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* f1100000 11000000 System controller registers
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* f1200000 12000000 EBI registers
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* f1300000 13000000 Counter/Timer
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* f1400000 14000000 Interrupt controller
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* f1600000 16000000 UART 0
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* f1700000 17000000 UART 1
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* f1a00000 1a000000 Debug LEDs
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* fc900000 c9000000 GPIO
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* fca00000 ca000000 SIC
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* fcb00000 cb000000 CP system control
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*/
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static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
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{
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.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}
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};
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static void __init intcp_map_io(void)
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{
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iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
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}
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/*
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* Flash handling.
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*/
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static int intcp_flash_init(struct platform_device *dev)
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{
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u32 val;
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val = readl(intcp_con_base + INTCP_FLASHPROG);
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val |= CINTEGRATOR_FLASHPROG_FLWREN;
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writel(val, intcp_con_base + INTCP_FLASHPROG);
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return 0;
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}
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static void intcp_flash_exit(struct platform_device *dev)
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{
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u32 val;
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val = readl(intcp_con_base + INTCP_FLASHPROG);
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val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
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writel(val, intcp_con_base + INTCP_FLASHPROG);
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}
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static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
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{
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u32 val;
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val = readl(intcp_con_base + INTCP_FLASHPROG);
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if (on)
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val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
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else
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val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
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writel(val, intcp_con_base + INTCP_FLASHPROG);
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}
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static struct physmap_flash_data intcp_flash_data = {
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.width = 4,
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.init = intcp_flash_init,
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.exit = intcp_flash_exit,
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.set_vpp = intcp_flash_set_vpp,
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};
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/*
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* It seems that the card insertion interrupt remains active after
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* we've acknowledged it. We therefore ignore the interrupt, and
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* rely on reading it from the SIC. This also means that we must
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* clear the latched interrupt.
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*/
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static unsigned int mmc_status(struct device *dev)
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{
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unsigned int status = readl(__io_address(0xca000000 + 4));
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writel(8, intcp_con_base + 8);
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return status & 8;
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}
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static struct mmci_platform_data mmc_data = {
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.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
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.status = mmc_status,
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.gpio_wp = -1,
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.gpio_cd = -1,
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};
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/*
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* CLCD support
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*/
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/*
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* Ensure VGA is selected.
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*/
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static void cp_clcd_enable(struct clcd_fb *fb)
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{
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struct fb_var_screeninfo *var = &fb->fb.var;
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u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
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if (var->bits_per_pixel <= 8 ||
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(var->bits_per_pixel == 16 && var->green.length == 5))
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/* Pseudocolor, RGB555, BGR555 */
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val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
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else if (fb->fb.var.bits_per_pixel <= 16)
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/* truecolor RGB565 */
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val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
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else
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val = 0; /* no idea for this, don't trust the docs */
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cm_control(CM_CTRL_LCDMUXSEL_MASK|
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CM_CTRL_LCDEN0|
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CM_CTRL_LCDEN1|
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CM_CTRL_STATIC1|
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CM_CTRL_STATIC2|
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CM_CTRL_STATIC|
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CM_CTRL_n24BITEN, val);
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}
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static int cp_clcd_setup(struct clcd_fb *fb)
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{
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fb->panel = versatile_clcd_get_panel("VGA");
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if (!fb->panel)
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return -EINVAL;
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return versatile_clcd_setup_dma(fb, SZ_1M);
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}
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static struct clcd_board clcd_data = {
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.name = "Integrator/CP",
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.caps = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
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.check = clcdfb_check,
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.decode = clcdfb_decode,
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.enable = cp_clcd_enable,
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.setup = cp_clcd_setup,
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.mmap = versatile_clcd_mmap_dma,
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.remove = versatile_clcd_remove_dma,
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};
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#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
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static void __init intcp_init_early(void)
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{
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#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
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versatile_sched_clock_init(REFCOUNTER, 24000000);
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#endif
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}
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#ifdef CONFIG_OF
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static void __init cp_of_timer_init(void)
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{
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struct device_node *node;
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const char *path;
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void __iomem *base;
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int err;
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int irq;
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err = of_property_read_string(of_aliases,
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"arm,timer-primary", &path);
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if (WARN_ON(err))
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return;
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node = of_find_node_by_path(path);
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base = of_iomap(node, 0);
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if (WARN_ON(!base))
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return;
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writel(0, base + TIMER_CTRL);
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sp804_clocksource_init(base, node->name);
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err = of_property_read_string(of_aliases,
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"arm,timer-secondary", &path);
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if (WARN_ON(err))
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return;
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node = of_find_node_by_path(path);
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base = of_iomap(node, 0);
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if (WARN_ON(!base))
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return;
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irq = irq_of_parse_and_map(node, 0);
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writel(0, base + TIMER_CTRL);
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sp804_clockevents_init(base, irq, node->name);
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}
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static const struct of_device_id fpga_irq_of_match[] __initconst = {
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{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
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{ /* Sentinel */ }
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};
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static void __init intcp_init_irq_of(void)
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{
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of_irq_init(fpga_irq_of_match);
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integrator_clk_init(true);
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}
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/*
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* For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
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* and enforce the bus names since these are used for clock lookups.
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*/
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static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
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"rtc", NULL),
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
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"uart0", NULL),
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
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"uart1", NULL),
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OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
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"kmi0", NULL),
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OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
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"kmi1", NULL),
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
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"mmci", &mmc_data),
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
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"aaci", &mmc_data),
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OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
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"clcd", &clcd_data),
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OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
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"physmap-flash", &intcp_flash_data),
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{ /* sentinel */ },
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};
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static void __init intcp_init_of(void)
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{
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struct device_node *root;
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struct device_node *cpcon;
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struct device *parent;
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struct soc_device *soc_dev;
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struct soc_device_attribute *soc_dev_attr;
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u32 intcp_sc_id;
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int err;
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/* Here we create an SoC device for the root node */
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root = of_find_node_by_path("/");
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if (!root)
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return;
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cpcon = of_find_node_by_path("/cpcon");
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if (!cpcon)
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return;
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intcp_con_base = of_iomap(cpcon, 0);
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if (!intcp_con_base)
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return;
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intcp_sc_id = readl(intcp_con_base);
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (!soc_dev_attr)
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return;
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err = of_property_read_string(root, "compatible",
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&soc_dev_attr->soc_id);
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if (err)
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return;
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err = of_property_read_string(root, "model", &soc_dev_attr->machine);
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if (err)
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return;
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soc_dev_attr->family = "Integrator";
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soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
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'A' + (intcp_sc_id & 0x0f));
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR_OR_NULL(soc_dev)) {
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kfree(soc_dev_attr->revision);
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kfree(soc_dev_attr);
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return;
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}
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parent = soc_device_to_device(soc_dev);
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if (!IS_ERR_OR_NULL(parent))
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integrator_init_sysfs(parent, intcp_sc_id);
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of_platform_populate(root, of_default_bus_match_table,
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intcp_auxdata_lookup, parent);
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}
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static const char * intcp_dt_board_compat[] = {
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"arm,integrator-cp",
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NULL,
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};
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DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
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.reserve = integrator_reserve,
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.map_io = intcp_map_io,
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.init_early = intcp_init_early,
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.init_irq = intcp_init_irq_of,
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.handle_irq = fpga_handle_irq,
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.init_time = cp_of_timer_init,
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.init_machine = intcp_init_of,
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.restart = integrator_restart,
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.dt_compat = intcp_dt_board_compat,
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MACHINE_END
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#endif
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#ifdef CONFIG_ATAGS
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/*
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* For the ATAG boot some static mappings are needed. This will
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* go away with the ATAG support down the road.
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*/
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static struct map_desc intcp_io_desc_atag[] __initdata = {
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{
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.virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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},
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};
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static void __init intcp_map_io_atag(void)
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{
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iotable_init(intcp_io_desc_atag, ARRAY_SIZE(intcp_io_desc_atag));
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intcp_con_base = __io_address(INTEGRATOR_CP_CTL_BASE);
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intcp_map_io();
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}
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/*
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* This is where non-devicetree initialization code is collected and stashed
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* for eventual deletion.
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*/
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#define INTCP_FLASH_SIZE SZ_32M
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static struct resource intcp_flash_resource = {
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.start = INTCP_PA_FLASH_BASE,
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.end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device intcp_flash_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &intcp_flash_data,
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},
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.num_resources = 1,
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.resource = &intcp_flash_resource,
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};
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#define INTCP_ETH_SIZE 0x10
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static struct resource smc91x_resources[] = {
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[0] = {
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.start = INTEGRATOR_CP_ETH_BASE,
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.end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_CP_ETHINT,
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.end = IRQ_CP_ETHINT,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device smc91x_device = {
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.name = "smc91x",
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.id = 0,
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.num_resources = ARRAY_SIZE(smc91x_resources),
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.resource = smc91x_resources,
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};
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static struct platform_device *intcp_devs[] __initdata = {
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&intcp_flash_device,
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&smc91x_device,
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};
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#define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40)
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#define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE)
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#define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE)
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static void __init intcp_init_irq(void)
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{
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u32 pic_mask, cic_mask, sic_mask;
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/* These masks are for the HW IRQ registers */
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pic_mask = ~((~0u) << (11 - 0));
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pic_mask |= (~((~0u) << (29 - 22))) << 22;
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cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
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sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
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/*
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* Disable all interrupt sources
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*/
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writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
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writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
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writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
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|
writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
|
|
writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
|
|
writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
|
|
|
|
fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
|
|
-1, pic_mask, NULL);
|
|
|
|
fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
|
|
-1, cic_mask, NULL);
|
|
|
|
fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
|
|
IRQ_CP_CPPLDINT, sic_mask, NULL);
|
|
|
|
integrator_clk_init(true);
|
|
}
|
|
|
|
#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
|
|
#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
|
|
#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
|
|
|
|
static void __init cp_timer_init(void)
|
|
{
|
|
writel(0, TIMER0_VA_BASE + TIMER_CTRL);
|
|
writel(0, TIMER1_VA_BASE + TIMER_CTRL);
|
|
writel(0, TIMER2_VA_BASE + TIMER_CTRL);
|
|
|
|
sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
|
|
sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
|
|
}
|
|
|
|
#define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
|
|
#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
|
|
|
|
static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
|
|
INTEGRATOR_CP_MMC_IRQS, &mmc_data);
|
|
|
|
static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
|
|
INTEGRATOR_CP_AACI_IRQS, NULL);
|
|
|
|
static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
|
|
{ IRQ_CP_CLCDCINT }, &clcd_data);
|
|
|
|
static struct amba_device *amba_devs[] __initdata = {
|
|
&mmc_device,
|
|
&aaci_device,
|
|
&clcd_device,
|
|
};
|
|
|
|
static void __init intcp_init(void)
|
|
{
|
|
int i;
|
|
|
|
platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
|
|
|
|
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
|
|
struct amba_device *d = amba_devs[i];
|
|
amba_device_register(d, &iomem_resource);
|
|
}
|
|
integrator_init(true);
|
|
}
|
|
|
|
MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
|
|
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
|
|
.atag_offset = 0x100,
|
|
.reserve = integrator_reserve,
|
|
.map_io = intcp_map_io_atag,
|
|
.init_early = intcp_init_early,
|
|
.init_irq = intcp_init_irq,
|
|
.handle_irq = fpga_handle_irq,
|
|
.init_time = cp_timer_init,
|
|
.init_machine = intcp_init,
|
|
.restart = integrator_restart,
|
|
MACHINE_END
|
|
|
|
#endif
|