251 lines
7.8 KiB
C
251 lines
7.8 KiB
C
/*
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* OMAP Dual-Mode Timers
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
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* Tarun Kanti DebBarma <tarun.kanti@ti.com>
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* Thara Gopinath <thara@ti.com>
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*
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* Platform device conversion and hwmod support.
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*
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* Copyright (C) 2005 Nokia Corporation
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* Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
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* PWM and clock framwork support by Timo Teras.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#ifndef __CLOCKSOURCE_DMTIMER_H
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#define __CLOCKSOURCE_DMTIMER_H
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/* clock sources */
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#define OMAP_TIMER_SRC_SYS_CLK 0x00
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#define OMAP_TIMER_SRC_32_KHZ 0x01
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#define OMAP_TIMER_SRC_EXT_CLK 0x02
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/* timer interrupt enable bits */
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#define OMAP_TIMER_INT_CAPTURE (1 << 2)
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#define OMAP_TIMER_INT_OVERFLOW (1 << 1)
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#define OMAP_TIMER_INT_MATCH (1 << 0)
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/* trigger types */
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#define OMAP_TIMER_TRIGGER_NONE 0x00
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#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
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#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
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/* posted mode types */
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#define OMAP_TIMER_NONPOSTED 0x00
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#define OMAP_TIMER_POSTED 0x01
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/* timer capabilities used in hwmod database */
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#define OMAP_TIMER_SECURE 0x80000000
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#define OMAP_TIMER_ALWON 0x40000000
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#define OMAP_TIMER_HAS_PWM 0x20000000
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#define OMAP_TIMER_NEEDS_RESET 0x10000000
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#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
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/*
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* timer errata flags
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*
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* Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
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* errata prevents us from using posted mode on these devices, unless the
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* timer counter register is never read. For more details please refer to
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* the OMAP3/4/5 errata documents.
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*/
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#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
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struct timer_regs {
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u32 ocp_cfg;
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u32 tidr;
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u32 tier;
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u32 twer;
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u32 tclr;
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u32 tcrr;
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u32 tldr;
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u32 ttrg;
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u32 twps;
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u32 tmar;
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u32 tcar1;
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u32 tsicr;
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u32 tcar2;
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u32 tpir;
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u32 tnir;
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u32 tcvr;
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u32 tocr;
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u32 towr;
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};
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struct omap_dm_timer {
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int id;
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int irq;
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struct clk *fclk;
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void __iomem *io_base;
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void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
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void __iomem *irq_ena; /* irq enable */
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void __iomem *irq_dis; /* irq disable, only on v2 ip */
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void __iomem *pend; /* write pending */
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void __iomem *func_base; /* function register base */
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atomic_t enabled;
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unsigned long rate;
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unsigned reserved:1;
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unsigned posted:1;
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struct timer_regs context;
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int revision;
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u32 capability;
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u32 errata;
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struct platform_device *pdev;
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struct list_head node;
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struct notifier_block nb;
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};
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int omap_dm_timer_reserve_systimer(int id);
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struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
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int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
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u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
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int omap_dm_timer_trigger(struct omap_dm_timer *timer);
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int omap_dm_timers_active(void);
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/*
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* Do not use the defines below, they are not needed. They should be only
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* used by dmtimer.c and sys_timer related code.
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*/
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/*
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* The interrupt registers are different between v1 and v2 ip.
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* These registers are offsets from timer->iobase.
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*/
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#define OMAP_TIMER_ID_OFFSET 0x00
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#define OMAP_TIMER_OCP_CFG_OFFSET 0x10
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#define OMAP_TIMER_V1_SYS_STAT_OFFSET 0x14
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#define OMAP_TIMER_V1_STAT_OFFSET 0x18
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#define OMAP_TIMER_V1_INT_EN_OFFSET 0x1c
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#define OMAP_TIMER_V2_IRQSTATUS_RAW 0x24
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#define OMAP_TIMER_V2_IRQSTATUS 0x28
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#define OMAP_TIMER_V2_IRQENABLE_SET 0x2c
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#define OMAP_TIMER_V2_IRQENABLE_CLR 0x30
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/*
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* The functional registers have a different base on v1 and v2 ip.
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* These registers are offsets from timer->func_base. The func_base
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* is samae as io_base for v1 and io_base + 0x14 for v2 ip.
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*
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*/
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#define OMAP_TIMER_V2_FUNC_OFFSET 0x14
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#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
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#define _OMAP_TIMER_CTRL_OFFSET 0x24
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#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
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#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
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#define OMAP_TIMER_CTRL_PT (1 << 12)
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#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
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#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
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#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
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#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
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#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
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#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
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#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
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#define OMAP_TIMER_CTRL_POSTED (1 << 2)
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#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
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#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
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#define _OMAP_TIMER_COUNTER_OFFSET 0x28
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#define _OMAP_TIMER_LOAD_OFFSET 0x2c
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#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
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#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
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#define WP_NONE 0 /* no write pending bit */
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#define WP_TCLR (1 << 0)
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#define WP_TCRR (1 << 1)
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#define WP_TLDR (1 << 2)
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#define WP_TTGR (1 << 3)
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#define WP_TMAR (1 << 4)
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#define WP_TPIR (1 << 5)
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#define WP_TNIR (1 << 6)
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#define WP_TCVR (1 << 7)
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#define WP_TOCR (1 << 8)
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#define WP_TOWR (1 << 9)
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#define _OMAP_TIMER_MATCH_OFFSET 0x38
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#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
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#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
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#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
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#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
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#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
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#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
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#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
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#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
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/* register offsets with the write pending bit encoded */
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#define WPSHIFT 16
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#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
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| (WP_TCLR << WPSHIFT))
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#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
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| (WP_TCRR << WPSHIFT))
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#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
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| (WP_TLDR << WPSHIFT))
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#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
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| (WP_TTGR << WPSHIFT))
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#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
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| (WP_TMAR << WPSHIFT))
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#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
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| (WP_NONE << WPSHIFT))
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#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
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| (WP_TPIR << WPSHIFT))
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#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
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| (WP_TNIR << WPSHIFT))
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#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
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| (WP_TCVR << WPSHIFT))
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#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
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(_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
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#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
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(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
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#endif /* __CLOCKSOURCE_DMTIMER_H */
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