210 lines
5.0 KiB
ArmAsm
210 lines
5.0 KiB
ArmAsm
/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/linkage.h>
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#include <asm/alternative.h>
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#include <asm/assembler.h>
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#include <asm/cpufeature.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_mmu.h>
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.text
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.pushsection .hyp.text, "ax"
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.macro do_el2_call
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/*
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* Shuffle the parameters before calling the function
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* pointed to in x0. Assumes parameters in x[1,2,3].
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*/
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str lr, [sp, #-16]!
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mov lr, x0
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mov x0, x1
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mov x1, x2
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mov x2, x3
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blr lr
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ldr lr, [sp], #16
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.endm
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ENTRY(__vhe_hyp_call)
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do_el2_call
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/*
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* We used to rely on having an exception return to get
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* an implicit isb. In the E2H case, we don't have it anymore.
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* rather than changing all the leaf functions, just do it here
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* before returning to the rest of the kernel.
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*/
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isb
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ret
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ENDPROC(__vhe_hyp_call)
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el1_sync: // Guest trapped into EL2
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stp x0, x1, [sp, #-16]!
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alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
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mrs x1, esr_el2
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alternative_else
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mrs x1, esr_el1
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alternative_endif
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lsr x0, x1, #ESR_ELx_EC_SHIFT
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cmp x0, #ESR_ELx_EC_HVC64
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b.ne el1_trap
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mrs x1, vttbr_el2 // If vttbr is valid, the 64bit guest
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cbnz x1, el1_trap // called HVC
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/* Here, we're pretty sure the host called HVC. */
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ldp x0, x1, [sp], #16
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/* Check for a stub HVC call */
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cmp x0, #HVC_STUB_HCALL_NR
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b.hs 1f
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/*
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* Compute the idmap address of __kvm_handle_stub_hvc and
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* jump there. Since we use kimage_voffset, do not use the
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* HYP VA for __kvm_handle_stub_hvc, but the kernel VA instead
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* (by loading it from the constant pool).
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*
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* Preserve x0-x4, which may contain stub parameters.
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*/
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ldr x5, =__kvm_handle_stub_hvc
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ldr_l x6, kimage_voffset
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/* x5 = __pa(x5) */
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sub x5, x5, x6
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br x5
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1:
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/*
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* Perform the EL2 call
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*/
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kern_hyp_va x0
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do_el2_call
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eret
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el1_trap:
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/*
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* x0: ESR_EC
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*/
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/*
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* We trap the first access to the FP/SIMD to save the host context
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* and restore the guest context lazily.
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* If FP/SIMD is not implemented, handle the trap and inject an
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* undefined instruction exception to the guest.
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*/
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alternative_if_not ARM64_HAS_NO_FPSIMD
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cmp x0, #ESR_ELx_EC_FP_ASIMD
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b.eq __fpsimd_guest_restore
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alternative_else_nop_endif
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mrs x1, tpidr_el2
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mov x0, #ARM_EXCEPTION_TRAP
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b __guest_exit
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el1_irq:
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stp x0, x1, [sp, #-16]!
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mrs x1, tpidr_el2
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mov x0, #ARM_EXCEPTION_IRQ
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b __guest_exit
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el1_error:
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stp x0, x1, [sp, #-16]!
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mrs x1, tpidr_el2
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mov x0, #ARM_EXCEPTION_EL1_SERROR
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b __guest_exit
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el2_error:
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/*
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* Only two possibilities:
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* 1) Either we come from the exit path, having just unmasked
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* PSTATE.A: change the return code to an EL2 fault, and
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* carry on, as we're already in a sane state to handle it.
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* 2) Or we come from anywhere else, and that's a bug: we panic.
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*
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* For (1), x0 contains the original return code and x1 doesn't
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* contain anything meaningful at that stage. We can reuse them
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* as temp registers.
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* For (2), who cares?
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*/
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mrs x0, elr_el2
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adr x1, abort_guest_exit_start
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cmp x0, x1
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adr x1, abort_guest_exit_end
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ccmp x0, x1, #4, ne
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b.ne __hyp_panic
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mov x0, #(1 << ARM_EXIT_WITH_SERROR_BIT)
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eret
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ENTRY(__hyp_do_panic)
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mov lr, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
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PSR_MODE_EL1h)
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msr spsr_el2, lr
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ldr lr, =panic
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msr elr_el2, lr
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eret
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ENDPROC(__hyp_do_panic)
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.macro invalid_vector label, target = __hyp_panic
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.align 2
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\label:
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b \target
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ENDPROC(\label)
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.endm
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/* None of these should ever happen */
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invalid_vector el2t_sync_invalid
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invalid_vector el2t_irq_invalid
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invalid_vector el2t_fiq_invalid
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invalid_vector el2t_error_invalid
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invalid_vector el2h_sync_invalid
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invalid_vector el2h_irq_invalid
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invalid_vector el2h_fiq_invalid
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invalid_vector el1_sync_invalid
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invalid_vector el1_irq_invalid
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invalid_vector el1_fiq_invalid
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.ltorg
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.align 11
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ENTRY(__kvm_hyp_vector)
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ventry el2t_sync_invalid // Synchronous EL2t
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ventry el2t_irq_invalid // IRQ EL2t
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ventry el2t_fiq_invalid // FIQ EL2t
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ventry el2t_error_invalid // Error EL2t
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ventry el2h_sync_invalid // Synchronous EL2h
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ventry el2h_irq_invalid // IRQ EL2h
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ventry el2h_fiq_invalid // FIQ EL2h
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ventry el2_error // Error EL2h
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ventry el1_sync // Synchronous 64-bit EL1
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ventry el1_irq // IRQ 64-bit EL1
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ventry el1_fiq_invalid // FIQ 64-bit EL1
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ventry el1_error // Error 64-bit EL1
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ventry el1_sync // Synchronous 32-bit EL1
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ventry el1_irq // IRQ 32-bit EL1
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ventry el1_fiq_invalid // FIQ 32-bit EL1
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ventry el1_error // Error 32-bit EL1
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ENDPROC(__kvm_hyp_vector)
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