343 lines
8.3 KiB
C
343 lines
8.3 KiB
C
/*
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* Copyright (C) STMicroelectronics 2016
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*
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* Author: Benjamin Gaignard <benjamin.gaignard@st.com>
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*
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* License terms: GNU General Public License (GPL), version 2
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*/
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include <linux/iio/timer/stm32-timer-trigger.h>
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#include <linux/iio/trigger.h>
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#include <linux/mfd/stm32-timers.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#define MAX_TRIGGERS 6
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/* List the triggers created by each timer */
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static const void *triggers_table[][MAX_TRIGGERS] = {
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{ TIM1_TRGO, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
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{ TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
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{ TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
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{ TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
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{ TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
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{ TIM6_TRGO,},
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{ TIM7_TRGO,},
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{ TIM8_TRGO, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
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{ TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
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{ }, /* timer 10 */
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{ }, /* timer 11 */
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{ TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
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};
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struct stm32_timer_trigger {
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struct device *dev;
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struct regmap *regmap;
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struct clk *clk;
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u32 max_arr;
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const void *triggers;
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};
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static int stm32_timer_start(struct stm32_timer_trigger *priv,
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unsigned int frequency)
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{
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unsigned long long prd, div;
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int prescaler = 0;
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u32 ccer, cr1;
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/* Period and prescaler values depends of clock rate */
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div = (unsigned long long)clk_get_rate(priv->clk);
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do_div(div, frequency);
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prd = div;
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/*
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* Increase prescaler value until we get a result that fit
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* with auto reload register maximum value.
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*/
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while (div > priv->max_arr) {
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prescaler++;
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div = prd;
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do_div(div, (prescaler + 1));
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}
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prd = div;
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if (prescaler > MAX_TIM_PSC) {
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dev_err(priv->dev, "prescaler exceeds the maximum value\n");
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return -EINVAL;
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}
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/* Check if nobody else use the timer */
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regmap_read(priv->regmap, TIM_CCER, &ccer);
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if (ccer & TIM_CCER_CCXE)
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return -EBUSY;
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regmap_read(priv->regmap, TIM_CR1, &cr1);
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if (!(cr1 & TIM_CR1_CEN))
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clk_enable(priv->clk);
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regmap_write(priv->regmap, TIM_PSC, prescaler);
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regmap_write(priv->regmap, TIM_ARR, prd - 1);
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
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/* Force master mode to update mode */
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regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0x20);
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/* Make sure that registers are updated */
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regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
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/* Enable controller */
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
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return 0;
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}
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static void stm32_timer_stop(struct stm32_timer_trigger *priv)
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{
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u32 ccer, cr1;
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regmap_read(priv->regmap, TIM_CCER, &ccer);
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if (ccer & TIM_CCER_CCXE)
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return;
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regmap_read(priv->regmap, TIM_CR1, &cr1);
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if (cr1 & TIM_CR1_CEN)
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clk_disable(priv->clk);
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/* Stop timer */
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regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
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regmap_write(priv->regmap, TIM_PSC, 0);
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regmap_write(priv->regmap, TIM_ARR, 0);
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/* Make sure that registers are updated */
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regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
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}
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static ssize_t stm32_tt_store_frequency(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t len)
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{
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struct iio_trigger *trig = to_iio_trigger(dev);
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struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
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unsigned int freq;
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int ret;
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ret = kstrtouint(buf, 10, &freq);
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if (ret)
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return ret;
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if (freq == 0) {
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stm32_timer_stop(priv);
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} else {
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ret = stm32_timer_start(priv, freq);
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if (ret)
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return ret;
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}
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return len;
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}
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static ssize_t stm32_tt_read_frequency(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct iio_trigger *trig = to_iio_trigger(dev);
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struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
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u32 psc, arr, cr1;
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unsigned long long freq = 0;
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regmap_read(priv->regmap, TIM_CR1, &cr1);
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regmap_read(priv->regmap, TIM_PSC, &psc);
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regmap_read(priv->regmap, TIM_ARR, &arr);
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if (psc && arr && (cr1 & TIM_CR1_CEN)) {
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freq = (unsigned long long)clk_get_rate(priv->clk);
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do_div(freq, psc);
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do_div(freq, arr);
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}
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return sprintf(buf, "%d\n", (unsigned int)freq);
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}
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static IIO_DEV_ATTR_SAMP_FREQ(0660,
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stm32_tt_read_frequency,
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stm32_tt_store_frequency);
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static char *master_mode_table[] = {
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"reset",
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"enable",
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"update",
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"compare_pulse",
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"OC1REF",
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"OC2REF",
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"OC3REF",
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"OC4REF"
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};
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static ssize_t stm32_tt_show_master_mode(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct stm32_timer_trigger *priv = iio_priv(indio_dev);
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u32 cr2;
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regmap_read(priv->regmap, TIM_CR2, &cr2);
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cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
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return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
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}
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static ssize_t stm32_tt_store_master_mode(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t len)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct stm32_timer_trigger *priv = iio_priv(indio_dev);
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int i;
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for (i = 0; i < ARRAY_SIZE(master_mode_table); i++) {
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if (!strncmp(master_mode_table[i], buf,
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strlen(master_mode_table[i]))) {
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regmap_update_bits(priv->regmap, TIM_CR2,
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TIM_CR2_MMS, i << TIM_CR2_MMS_SHIFT);
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/* Make sure that registers are updated */
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regmap_update_bits(priv->regmap, TIM_EGR,
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TIM_EGR_UG, TIM_EGR_UG);
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return len;
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}
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}
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return -EINVAL;
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}
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static IIO_CONST_ATTR(master_mode_available,
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"reset enable update compare_pulse OC1REF OC2REF OC3REF OC4REF");
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static IIO_DEVICE_ATTR(master_mode, 0660,
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stm32_tt_show_master_mode,
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stm32_tt_store_master_mode,
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0);
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static struct attribute *stm32_trigger_attrs[] = {
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&iio_dev_attr_sampling_frequency.dev_attr.attr,
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&iio_dev_attr_master_mode.dev_attr.attr,
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&iio_const_attr_master_mode_available.dev_attr.attr,
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NULL,
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};
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static const struct attribute_group stm32_trigger_attr_group = {
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.attrs = stm32_trigger_attrs,
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};
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static const struct attribute_group *stm32_trigger_attr_groups[] = {
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&stm32_trigger_attr_group,
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NULL,
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};
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static const struct iio_trigger_ops timer_trigger_ops = {
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.owner = THIS_MODULE,
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};
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static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
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{
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int ret;
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const char * const *cur = priv->triggers;
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while (cur && *cur) {
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struct iio_trigger *trig;
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trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
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if (!trig)
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return -ENOMEM;
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trig->dev.parent = priv->dev->parent;
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trig->ops = &timer_trigger_ops;
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/*
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* sampling frequency and master mode attributes
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* should only be available on trgo trigger which
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* is always the first in the list.
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*/
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if (cur == priv->triggers)
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trig->dev.groups = stm32_trigger_attr_groups;
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iio_trigger_set_drvdata(trig, priv);
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ret = devm_iio_trigger_register(priv->dev, trig);
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if (ret)
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return ret;
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cur++;
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}
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return 0;
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}
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/**
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* is_stm32_timer_trigger
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* @trig: trigger to be checked
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*
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* return true if the trigger is a valid stm32 iio timer trigger
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* either return false
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*/
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bool is_stm32_timer_trigger(struct iio_trigger *trig)
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{
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return (trig->ops == &timer_trigger_ops);
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}
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EXPORT_SYMBOL(is_stm32_timer_trigger);
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static int stm32_timer_trigger_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct stm32_timer_trigger *priv;
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struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
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unsigned int index;
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int ret;
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if (of_property_read_u32(dev->of_node, "reg", &index))
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return -EINVAL;
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if (index >= ARRAY_SIZE(triggers_table))
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return -EINVAL;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->dev = dev;
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priv->regmap = ddata->regmap;
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priv->clk = ddata->clk;
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priv->max_arr = ddata->max_arr;
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priv->triggers = triggers_table[index];
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ret = stm32_setup_iio_triggers(priv);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, priv);
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return 0;
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}
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static const struct of_device_id stm32_trig_of_match[] = {
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{ .compatible = "st,stm32-timer-trigger", },
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{ /* end node */ },
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};
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MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
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static struct platform_driver stm32_timer_trigger_driver = {
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.probe = stm32_timer_trigger_probe,
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.driver = {
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.name = "stm32-timer-trigger",
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.of_match_table = stm32_trig_of_match,
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},
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};
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module_platform_driver(stm32_timer_trigger_driver);
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MODULE_ALIAS("platform: stm32-timer-trigger");
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MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
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MODULE_LICENSE("GPL v2");
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