182 lines
6.4 KiB
C
182 lines
6.4 KiB
C
/*
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* (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
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* Author: Liviu Dudau <Liviu.Dudau@arm.com>
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU licence.
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*
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* ARM Mali DP500/DP550/DP650 registers definition.
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*/
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#ifndef __MALIDP_REGS_H__
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#define __MALIDP_REGS_H__
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/*
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* abbreviations used:
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* - DC - display core (general settings)
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* - DE - display engine
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* - SE - scaling engine
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*/
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/* interrupt bit masks */
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#define MALIDP_DE_IRQ_UNDERRUN (1 << 0)
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#define MALIDP500_DE_IRQ_AXI_ERR (1 << 4)
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#define MALIDP500_DE_IRQ_VSYNC (1 << 5)
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#define MALIDP500_DE_IRQ_PROG_LINE (1 << 6)
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#define MALIDP500_DE_IRQ_SATURATION (1 << 7)
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#define MALIDP500_DE_IRQ_CONF_VALID (1 << 8)
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#define MALIDP500_DE_IRQ_CONF_MODE (1 << 11)
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#define MALIDP500_DE_IRQ_CONF_ACTIVE (1 << 17)
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#define MALIDP500_DE_IRQ_PM_ACTIVE (1 << 18)
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#define MALIDP500_DE_IRQ_TESTMODE_ACTIVE (1 << 19)
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#define MALIDP500_DE_IRQ_FORCE_BLNK_ACTIVE (1 << 24)
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#define MALIDP500_DE_IRQ_AXI_BUSY (1 << 28)
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#define MALIDP500_DE_IRQ_GLOBAL (1 << 31)
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#define MALIDP500_SE_IRQ_CONF_MODE (1 << 0)
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#define MALIDP500_SE_IRQ_CONF_VALID (1 << 4)
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#define MALIDP500_SE_IRQ_INIT_BUSY (1 << 5)
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#define MALIDP500_SE_IRQ_AXI_ERROR (1 << 8)
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#define MALIDP500_SE_IRQ_OVERRUN (1 << 9)
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#define MALIDP500_SE_IRQ_PROG_LINE1 (1 << 12)
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#define MALIDP500_SE_IRQ_PROG_LINE2 (1 << 13)
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#define MALIDP500_SE_IRQ_CONF_ACTIVE (1 << 17)
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#define MALIDP500_SE_IRQ_PM_ACTIVE (1 << 18)
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#define MALIDP500_SE_IRQ_AXI_BUSY (1 << 28)
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#define MALIDP500_SE_IRQ_GLOBAL (1 << 31)
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#define MALIDP550_DE_IRQ_SATURATION (1 << 8)
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#define MALIDP550_DE_IRQ_VSYNC (1 << 12)
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#define MALIDP550_DE_IRQ_PROG_LINE (1 << 13)
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#define MALIDP550_DE_IRQ_AXI_ERR (1 << 16)
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#define MALIDP550_SE_IRQ_EOW (1 << 0)
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#define MALIDP550_SE_IRQ_AXI_ERR (1 << 16)
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#define MALIDP550_DC_IRQ_CONF_VALID (1 << 0)
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#define MALIDP550_DC_IRQ_CONF_MODE (1 << 4)
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#define MALIDP550_DC_IRQ_CONF_ACTIVE (1 << 16)
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#define MALIDP550_DC_IRQ_DE (1 << 20)
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#define MALIDP550_DC_IRQ_SE (1 << 24)
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#define MALIDP650_DE_IRQ_DRIFT (1 << 4)
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/* bit masks that are common between products */
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#define MALIDP_CFG_VALID (1 << 0)
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#define MALIDP_DISP_FUNC_ILACED (1 << 8)
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/* register offsets for IRQ management */
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#define MALIDP_REG_STATUS 0x00000
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#define MALIDP_REG_SETIRQ 0x00004
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#define MALIDP_REG_MASKIRQ 0x00008
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#define MALIDP_REG_CLEARIRQ 0x0000c
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/* register offsets */
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#define MALIDP_DE_CORE_ID 0x00018
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#define MALIDP_DE_DISPLAY_FUNC 0x00020
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/* these offsets are relative to MALIDP5x0_TIMINGS_BASE */
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#define MALIDP_DE_H_TIMINGS 0x0
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#define MALIDP_DE_V_TIMINGS 0x4
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#define MALIDP_DE_SYNC_WIDTH 0x8
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#define MALIDP_DE_HV_ACTIVE 0xc
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/* Stride register offsets relative to Lx_BASE */
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#define MALIDP_DE_LG_STRIDE 0x18
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#define MALIDP_DE_LV_STRIDE0 0x18
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#define MALIDP550_DE_LS_R1_STRIDE 0x28
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/* macros to set values into registers */
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#define MALIDP_DE_H_FRONTPORCH(x) (((x) & 0xfff) << 0)
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#define MALIDP_DE_H_BACKPORCH(x) (((x) & 0x3ff) << 16)
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#define MALIDP500_DE_V_FRONTPORCH(x) (((x) & 0xff) << 0)
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#define MALIDP550_DE_V_FRONTPORCH(x) (((x) & 0xfff) << 0)
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#define MALIDP_DE_V_BACKPORCH(x) (((x) & 0xff) << 16)
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#define MALIDP_DE_H_SYNCWIDTH(x) (((x) & 0x3ff) << 0)
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#define MALIDP_DE_V_SYNCWIDTH(x) (((x) & 0xff) << 16)
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#define MALIDP_DE_H_ACTIVE(x) (((x) & 0x1fff) << 0)
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#define MALIDP_DE_V_ACTIVE(x) (((x) & 0x1fff) << 16)
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#define MALIDP_PRODUCT_ID(__core_id) ((u32)(__core_id) >> 16)
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/* register offsets and bits specific to DP500 */
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#define MALIDP500_ADDR_SPACE_SIZE 0x01000
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#define MALIDP500_DC_BASE 0x00000
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#define MALIDP500_DC_CONTROL 0x0000c
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#define MALIDP500_DC_CONFIG_REQ (1 << 17)
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#define MALIDP500_HSYNCPOL (1 << 20)
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#define MALIDP500_VSYNCPOL (1 << 21)
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#define MALIDP500_DC_CLEAR_MASK 0x300fff
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#define MALIDP500_DE_LINE_COUNTER 0x00010
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#define MALIDP500_DE_AXI_CONTROL 0x00014
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#define MALIDP500_DE_SECURE_CTRL 0x0001c
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#define MALIDP500_DE_CHROMA_KEY 0x00024
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#define MALIDP500_TIMINGS_BASE 0x00028
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#define MALIDP500_CONFIG_3D 0x00038
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#define MALIDP500_BGND_COLOR 0x0003c
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#define MALIDP500_OUTPUT_DEPTH 0x00044
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#define MALIDP500_YUV_RGB_COEF 0x00048
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#define MALIDP500_COLOR_ADJ_COEF 0x00078
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#define MALIDP500_COEF_TABLE_ADDR 0x000a8
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#define MALIDP500_COEF_TABLE_DATA 0x000ac
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#define MALIDP500_DE_LV_BASE 0x00100
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#define MALIDP500_DE_LV_PTR_BASE 0x00124
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#define MALIDP500_DE_LG1_BASE 0x00200
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#define MALIDP500_DE_LG1_PTR_BASE 0x0021c
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#define MALIDP500_DE_LG2_BASE 0x00300
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#define MALIDP500_DE_LG2_PTR_BASE 0x0031c
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#define MALIDP500_SE_BASE 0x00c00
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#define MALIDP500_SE_PTR_BASE 0x00e0c
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#define MALIDP500_DC_IRQ_BASE 0x00f00
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#define MALIDP500_CONFIG_VALID 0x00f00
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#define MALIDP500_CONFIG_ID 0x00fd4
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/* register offsets and bits specific to DP550/DP650 */
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#define MALIDP550_ADDR_SPACE_SIZE 0x10000
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#define MALIDP550_DE_CONTROL 0x00010
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#define MALIDP550_DE_LINE_COUNTER 0x00014
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#define MALIDP550_DE_AXI_CONTROL 0x00018
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#define MALIDP550_DE_QOS 0x0001c
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#define MALIDP550_TIMINGS_BASE 0x00030
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#define MALIDP550_HSYNCPOL (1 << 12)
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#define MALIDP550_VSYNCPOL (1 << 28)
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#define MALIDP550_DE_DISP_SIDEBAND 0x00040
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#define MALIDP550_DE_BGND_COLOR 0x00044
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#define MALIDP550_DE_OUTPUT_DEPTH 0x0004c
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#define MALIDP550_DE_COLOR_COEF 0x00050
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#define MALIDP550_DE_COEF_TABLE_ADDR 0x00080
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#define MALIDP550_DE_COEF_TABLE_DATA 0x00084
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#define MALIDP550_DE_LV1_BASE 0x00100
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#define MALIDP550_DE_LV1_PTR_BASE 0x00124
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#define MALIDP550_DE_LV2_BASE 0x00200
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#define MALIDP550_DE_LV2_PTR_BASE 0x00224
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#define MALIDP550_DE_LG_BASE 0x00300
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#define MALIDP550_DE_LG_PTR_BASE 0x0031c
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#define MALIDP550_DE_LS_BASE 0x00400
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#define MALIDP550_DE_LS_PTR_BASE 0x0042c
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#define MALIDP550_DE_PERF_BASE 0x00500
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#define MALIDP550_SE_BASE 0x08000
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#define MALIDP550_DC_BASE 0x0c000
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#define MALIDP550_DC_CONTROL 0x0c010
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#define MALIDP550_DC_CONFIG_REQ (1 << 16)
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#define MALIDP550_CONFIG_VALID 0x0c014
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#define MALIDP550_CONFIG_ID 0x0ffd4
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/*
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* Starting with DP550 the register map blocks has been standardised to the
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* following layout:
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*
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* Offset Block registers
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* 0x00000 Display Engine
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* 0x08000 Scaling Engine
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* 0x0c000 Display Core
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* 0x10000 Secure control
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*
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* The old DP500 IP mixes some DC with the DE registers, hence the need
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* for a mapping structure.
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*/
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#endif /* __MALIDP_REGS_H__ */
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