In the hip06 and hip07 SoCs, the interrupt lines from the SAS
controllers are connected to mbigen hw module [1]. The mbigen module is
probed with module_init, and, as such, is not guaranteed to probe before
the SAS driver. So we need to support deferred probe.
We check for probe deferral in the hw layer probe, so we not probe into
the main layer and allocate shost, memories, etc., to later learn that
we need to defer the probe.
[1] ./Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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