210 lines
5.3 KiB
C
210 lines
5.3 KiB
C
/*
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* Device Tree support for Armada 370 and XP platforms.
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_address.h>
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#include <linux/of_fdt.h>
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#include <linux/io.h>
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#include <linux/clocksource.h>
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#include <linux/dma-mapping.h>
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#include <linux/memblock.h>
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#include <linux/mbus.h>
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#include <linux/slab.h>
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#include <linux/irqchip.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <asm/smp_scu.h>
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#include "armada-370-xp.h"
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#include "common.h"
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#include "coherency.h"
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#include "mvebu-soc-id.h"
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static void __iomem *scu_base;
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/*
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* Enables the SCU when available. Obviously, this is only useful on
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* Cortex-A based SOCs, not on PJ4B based ones.
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*/
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static void __init mvebu_scu_enable(void)
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{
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struct device_node *np =
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of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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if (np) {
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scu_base = of_iomap(np, 0);
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scu_enable(scu_base);
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of_node_put(np);
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}
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}
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void __iomem *mvebu_get_scu_base(void)
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{
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return scu_base;
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}
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/*
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* When returning from suspend, the platform goes through the
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* bootloader, which executes its DDR3 training code. This code has
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* the unfortunate idea of using the first 10 KB of each DRAM bank to
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* exercise the RAM and calculate the optimal timings. Therefore, this
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* area of RAM is overwritten, and shouldn't be used by the kernel if
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* suspend/resume is supported.
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*/
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#ifdef CONFIG_SUSPEND
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#define MVEBU_DDR_TRAINING_AREA_SZ (10 * SZ_1K)
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static int __init mvebu_scan_mem(unsigned long node, const char *uname,
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int depth, void *data)
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{
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const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
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const __be32 *reg, *endp;
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int l;
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if (type == NULL || strcmp(type, "memory"))
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return 0;
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reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
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if (reg == NULL)
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reg = of_get_flat_dt_prop(node, "reg", &l);
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if (reg == NULL)
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return 0;
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endp = reg + (l / sizeof(__be32));
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while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
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u64 base, size;
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base = dt_mem_next_cell(dt_root_addr_cells, ®);
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size = dt_mem_next_cell(dt_root_size_cells, ®);
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memblock_reserve(base, MVEBU_DDR_TRAINING_AREA_SZ);
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}
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return 0;
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}
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static void __init mvebu_memblock_reserve(void)
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{
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of_scan_flat_dt(mvebu_scan_mem, NULL);
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}
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#else
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static void __init mvebu_memblock_reserve(void) {}
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#endif
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static void __init mvebu_init_irq(void)
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{
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irqchip_init();
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mvebu_scu_enable();
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coherency_init();
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BUG_ON(mvebu_mbus_dt_init(coherency_available()));
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}
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static void __init i2c_quirk(void)
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{
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struct device_node *np;
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u32 dev, rev;
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/*
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* Only revisons more recent than A0 support the offload
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* mechanism. We can exit only if we are sure that we can
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* get the SoC revision and it is more recent than A0.
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*/
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if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > MV78XX0_A0_REV)
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return;
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for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") {
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struct property *new_compat;
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new_compat = kzalloc(sizeof(*new_compat), GFP_KERNEL);
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new_compat->name = kstrdup("compatible", GFP_KERNEL);
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new_compat->length = sizeof("marvell,mv78230-a0-i2c");
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new_compat->value = kstrdup("marvell,mv78230-a0-i2c",
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GFP_KERNEL);
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of_update_property(np, new_compat);
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}
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return;
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}
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static void __init mvebu_dt_init(void)
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{
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if (of_machine_is_compatible("marvell,armadaxp"))
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i2c_quirk();
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}
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static const char * const armada_370_xp_dt_compat[] __initconst = {
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"marvell,armada-370-xp",
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NULL,
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};
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DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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/*
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* The following field (.smp) is still needed to ensure backward
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* compatibility with old Device Trees that were not specifying the
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* cpus enable-method property.
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*/
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.smp = smp_ops(armada_xp_smp_ops),
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.init_machine = mvebu_dt_init,
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.init_irq = mvebu_init_irq,
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.restart = mvebu_restart,
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.reserve = mvebu_memblock_reserve,
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.dt_compat = armada_370_xp_dt_compat,
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MACHINE_END
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static const char * const armada_375_dt_compat[] __initconst = {
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"marvell,armada375",
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NULL,
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};
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DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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.init_irq = mvebu_init_irq,
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.init_machine = mvebu_dt_init,
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.restart = mvebu_restart,
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.dt_compat = armada_375_dt_compat,
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MACHINE_END
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static const char * const armada_38x_dt_compat[] __initconst = {
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"marvell,armada380",
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"marvell,armada385",
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NULL,
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};
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DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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.init_irq = mvebu_init_irq,
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.restart = mvebu_restart,
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.dt_compat = armada_38x_dt_compat,
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MACHINE_END
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static const char * const armada_39x_dt_compat[] __initconst = {
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"marvell,armada390",
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"marvell,armada398",
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NULL,
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};
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DT_MACHINE_START(ARMADA_39X_DT, "Marvell Armada 39x (Device Tree)")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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.init_irq = mvebu_init_irq,
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.restart = mvebu_restart,
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.dt_compat = armada_39x_dt_compat,
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MACHINE_END
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