158 lines
3.8 KiB
C
158 lines
3.8 KiB
C
/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <asm/sizes.h>
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#include "../hardware.h"
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#include "devices-common.h"
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#define imx_ahci_imx_data_entry_single(soc, _devid) \
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{ \
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.devid = _devid, \
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.iobase = soc ## _SATA_BASE_ADDR, \
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.irq = soc ## _INT_SATA, \
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}
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#ifdef CONFIG_SOC_IMX53
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const struct imx_ahci_imx_data imx53_ahci_imx_data __initconst =
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imx_ahci_imx_data_entry_single(MX53, "imx53-ahci");
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#endif
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enum {
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HOST_CAP = 0x00,
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HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
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HOST_PORTS_IMPL = 0x0c,
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HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
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};
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static struct clk *sata_clk, *sata_ref_clk;
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/* AHCI module Initialization, if return 0, initialization is successful. */
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static int imx_sata_init(struct device *dev, void __iomem *addr)
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{
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u32 tmpdata;
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int ret = 0;
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struct clk *clk;
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sata_clk = clk_get(dev, "ahci");
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if (IS_ERR(sata_clk)) {
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dev_err(dev, "no sata clock.\n");
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return PTR_ERR(sata_clk);
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}
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ret = clk_prepare_enable(sata_clk);
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if (ret) {
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dev_err(dev, "can't prepare/enable sata clock.\n");
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goto put_sata_clk;
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}
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/* Get the AHCI SATA PHY CLK */
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sata_ref_clk = clk_get(dev, "ahci_phy");
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if (IS_ERR(sata_ref_clk)) {
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dev_err(dev, "no sata ref clock.\n");
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ret = PTR_ERR(sata_ref_clk);
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goto release_sata_clk;
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}
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ret = clk_prepare_enable(sata_ref_clk);
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if (ret) {
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dev_err(dev, "can't prepare/enable sata ref clock.\n");
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goto put_sata_ref_clk;
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}
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/* Get the AHB clock rate, and configure the TIMER1MS reg later */
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clk = clk_get(dev, "ahci_dma");
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if (IS_ERR(clk)) {
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dev_err(dev, "no dma clock.\n");
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ret = PTR_ERR(clk);
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goto release_sata_ref_clk;
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}
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tmpdata = clk_get_rate(clk) / 1000;
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clk_put(clk);
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writel(tmpdata, addr + HOST_TIMER1MS);
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tmpdata = readl(addr + HOST_CAP);
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if (!(tmpdata & HOST_CAP_SSS)) {
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tmpdata |= HOST_CAP_SSS;
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writel(tmpdata, addr + HOST_CAP);
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}
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if (!(readl(addr + HOST_PORTS_IMPL) & 0x1))
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writel((readl(addr + HOST_PORTS_IMPL) | 0x1),
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addr + HOST_PORTS_IMPL);
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return 0;
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release_sata_ref_clk:
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clk_disable_unprepare(sata_ref_clk);
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put_sata_ref_clk:
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clk_put(sata_ref_clk);
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release_sata_clk:
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clk_disable_unprepare(sata_clk);
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put_sata_clk:
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clk_put(sata_clk);
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return ret;
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}
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static void imx_sata_exit(struct device *dev)
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{
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clk_disable_unprepare(sata_ref_clk);
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clk_put(sata_ref_clk);
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clk_disable_unprepare(sata_clk);
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clk_put(sata_clk);
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}
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struct platform_device *__init imx_add_ahci_imx(
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const struct imx_ahci_imx_data *data,
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const struct ahci_platform_data *pdata)
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{
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struct resource res[] = {
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{
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.start = data->iobase,
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.end = data->iobase + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = data->irq,
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.end = data->irq,
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.flags = IORESOURCE_IRQ,
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},
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};
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return imx_add_platform_device_dmamask(data->devid, 0,
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res, ARRAY_SIZE(res),
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pdata, sizeof(*pdata), DMA_BIT_MASK(32));
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}
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struct platform_device *__init imx53_add_ahci_imx(void)
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{
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struct ahci_platform_data pdata = {
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.init = imx_sata_init,
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.exit = imx_sata_exit,
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};
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return imx_add_ahci_imx(&imx53_ahci_imx_data, &pdata);
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}
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