256 lines
8.2 KiB
C
256 lines
8.2 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König
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*/
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#ifndef __AMDGPU_RING_H__
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#define __AMDGPU_RING_H__
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#include "gpu_scheduler.h"
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/* max number of rings */
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#define AMDGPU_MAX_RINGS 18
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#define AMDGPU_MAX_GFX_RINGS 1
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#define AMDGPU_MAX_COMPUTE_RINGS 8
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#define AMDGPU_MAX_VCE_RINGS 3
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#define AMDGPU_MAX_UVD_ENC_RINGS 2
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/* some special values for the owner field */
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#define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
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#define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
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#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
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#define AMDGPU_FENCE_FLAG_INT (1 << 1)
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enum amdgpu_ring_type {
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AMDGPU_RING_TYPE_GFX,
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AMDGPU_RING_TYPE_COMPUTE,
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AMDGPU_RING_TYPE_SDMA,
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AMDGPU_RING_TYPE_UVD,
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AMDGPU_RING_TYPE_VCE,
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AMDGPU_RING_TYPE_KIQ,
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AMDGPU_RING_TYPE_UVD_ENC,
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AMDGPU_RING_TYPE_VCN_DEC,
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AMDGPU_RING_TYPE_VCN_ENC
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};
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struct amdgpu_device;
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struct amdgpu_ring;
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struct amdgpu_ib;
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struct amdgpu_cs_parser;
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/*
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* Fences.
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*/
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struct amdgpu_fence_driver {
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uint64_t gpu_addr;
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volatile uint32_t *cpu_addr;
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/* sync_seq is protected by ring emission lock */
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uint32_t sync_seq;
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atomic_t last_seq;
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bool initialized;
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struct amdgpu_irq_src *irq_src;
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unsigned irq_type;
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struct timer_list fallback_timer;
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unsigned num_fences_mask;
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spinlock_t lock;
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struct dma_fence **fences;
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};
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int amdgpu_fence_driver_init(struct amdgpu_device *adev);
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void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
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void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
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void amdgpu_fence_driver_force_completion_ring(struct amdgpu_ring *ring);
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int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
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unsigned num_hw_submission);
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int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
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struct amdgpu_irq_src *irq_src,
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unsigned irq_type);
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void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
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void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
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int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence);
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void amdgpu_fence_process(struct amdgpu_ring *ring);
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int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
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unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
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/*
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* Rings.
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*/
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/* provided by hw blocks that expose a ring buffer for commands */
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struct amdgpu_ring_funcs {
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enum amdgpu_ring_type type;
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uint32_t align_mask;
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u32 nop;
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bool support_64bit_ptrs;
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unsigned vmhub;
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/* ring read/write ptr handling */
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u64 (*get_rptr)(struct amdgpu_ring *ring);
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u64 (*get_wptr)(struct amdgpu_ring *ring);
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void (*set_wptr)(struct amdgpu_ring *ring);
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/* validating and patching of IBs */
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int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
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/* constants to calculate how many DW are needed for an emit */
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unsigned emit_frame_size;
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unsigned emit_ib_size;
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/* command emit functions */
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void (*emit_ib)(struct amdgpu_ring *ring,
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struct amdgpu_ib *ib,
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unsigned vm_id, bool ctx_switch);
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void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
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uint64_t seq, unsigned flags);
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void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
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void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
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uint64_t pd_addr);
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void (*emit_hdp_flush)(struct amdgpu_ring *ring);
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void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);
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void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
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uint32_t gds_base, uint32_t gds_size,
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uint32_t gws_base, uint32_t gws_size,
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uint32_t oa_base, uint32_t oa_size);
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/* testing functions */
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int (*test_ring)(struct amdgpu_ring *ring);
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int (*test_ib)(struct amdgpu_ring *ring, long timeout);
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/* insert NOP packets */
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void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
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void (*insert_start)(struct amdgpu_ring *ring);
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void (*insert_end)(struct amdgpu_ring *ring);
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/* pad the indirect buffer to the necessary number of dw */
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void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
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unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
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void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset);
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/* note usage for clock and power gating */
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void (*begin_use)(struct amdgpu_ring *ring);
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void (*end_use)(struct amdgpu_ring *ring);
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void (*emit_switch_buffer) (struct amdgpu_ring *ring);
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void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
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void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
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void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
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void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
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};
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struct amdgpu_ring {
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struct amdgpu_device *adev;
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const struct amdgpu_ring_funcs *funcs;
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struct amdgpu_fence_driver fence_drv;
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struct amd_gpu_scheduler sched;
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struct list_head lru_list;
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struct amdgpu_bo *ring_obj;
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volatile uint32_t *ring;
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unsigned rptr_offs;
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u64 wptr;
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u64 wptr_old;
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unsigned ring_size;
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unsigned max_dw;
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int count_dw;
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uint64_t gpu_addr;
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uint64_t ptr_mask;
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uint32_t buf_mask;
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bool ready;
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u32 idx;
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u32 me;
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u32 pipe;
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u32 queue;
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struct amdgpu_bo *mqd_obj;
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uint64_t mqd_gpu_addr;
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void *mqd_ptr;
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uint64_t eop_gpu_addr;
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u32 doorbell_index;
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bool use_doorbell;
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unsigned wptr_offs;
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unsigned fence_offs;
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uint64_t current_ctx;
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char name[16];
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unsigned cond_exe_offs;
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u64 cond_exe_gpu_addr;
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volatile u32 *cond_exe_cpu_addr;
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unsigned vm_inv_eng;
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bool has_compute_vm_bug;
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#if defined(CONFIG_DEBUG_FS)
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struct dentry *ent;
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#endif
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};
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int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
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void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
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void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
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void amdgpu_ring_commit(struct amdgpu_ring *ring);
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void amdgpu_ring_undo(struct amdgpu_ring *ring);
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int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
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unsigned ring_size, struct amdgpu_irq_src *irq_src,
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unsigned irq_type);
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void amdgpu_ring_fini(struct amdgpu_ring *ring);
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int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type, int *blacklist,
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int num_blacklist, struct amdgpu_ring **ring);
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void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring);
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static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring)
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{
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int i = 0;
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while (i <= ring->buf_mask)
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ring->ring[i++] = ring->funcs->nop;
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}
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static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
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{
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if (ring->count_dw <= 0)
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DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
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ring->ring[ring->wptr++ & ring->buf_mask] = v;
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ring->wptr &= ring->ptr_mask;
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ring->count_dw--;
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}
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static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring,
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void *src, int count_dw)
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{
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unsigned occupied, chunk1, chunk2;
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void *dst;
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if (unlikely(ring->count_dw < count_dw))
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DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
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occupied = ring->wptr & ring->buf_mask;
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dst = (void *)&ring->ring[occupied];
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chunk1 = ring->buf_mask + 1 - occupied;
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chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
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chunk2 = count_dw - chunk1;
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chunk1 <<= 2;
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chunk2 <<= 2;
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if (chunk1)
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memcpy(dst, src, chunk1);
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if (chunk2) {
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src += chunk1;
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dst = (void *)ring->ring;
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memcpy(dst, src, chunk2);
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}
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ring->wptr += count_dw;
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ring->wptr &= ring->ptr_mask;
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ring->count_dw -= count_dw;
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}
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#endif
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