Fuyun Liang 5fd4789a98 net: hns3: refactor interrupt coalescing init function ... In the hardware, the coalesce configurable registers include GL0, GL1, GL2. In the driver, the TX queues use the register GL1 and the RX queues use the register GL0. This function initializes the configuration of the interrupt coalescing, but does not distinguish between the TX direction and the RX direction. It will cause some confusion. This patch refactors the function to initialize the TX GL and the RX GL separately. And the initialization of related variables also is added to this patch. Signed-off-by: Fuyun Liang <liangfuyun1@huawei.com> Signed-off-by: Peng Li <lipeng321@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>		2018-01-12 10:12:32 -05:00
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hns	net: hns: add ACPI mode support for ethtool -p	2018-01-02 14:50:39 -05:00
hns3	net: hns3: refactor interrupt coalescing init function	2018-01-12 10:12:32 -05:00
Kconfig	net: hns3: Add HNS3 VF driver to kernel build framework	2017-12-15 10:55:34 -05:00
Makefile	License cleanup: add SPDX GPL-2.0 license identifier to files with no license	2017-11-02 11:10:55 +01:00
hip04_eth.c	locking/atomics: COCCINELLE/treewide: Convert trivial ACCESS_ONCE() patterns to READ_ONCE()/WRITE_ONCE()	2017-10-25 11:01:08 +02:00
hisi_femac.c	drivers: net: generalize napi_complete_done()	2017-01-30 15:10:42 -05:00
hix5hd2_gmac.c	drivers: net: generalize napi_complete_done()	2017-01-30 15:10:42 -05:00
hns_mdio.c	net: hns: Fix a wrong op phy C45 code	2017-07-08 11:05:21 +01:00