258 lines
7.4 KiB
C
258 lines
7.4 KiB
C
#ifndef _ASM_IA64_TLB_H
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#define _ASM_IA64_TLB_H
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/*
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* Based on <asm-generic/tlb.h>.
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*
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* Copyright (C) 2002-2003 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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*/
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/*
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* Removing a translation from a page table (including TLB-shootdown) is a four-step
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* procedure:
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*
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* (1) Flush (virtual) caches --- ensures virtual memory is coherent with kernel memory
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* (this is a no-op on ia64).
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* (2) Clear the relevant portions of the page-table
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* (3) Flush the TLBs --- ensures that stale content is gone from CPU TLBs
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* (4) Release the pages that were freed up in step (2).
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*
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* Note that the ordering of these steps is crucial to avoid races on MP machines.
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*
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* The Linux kernel defines several platform-specific hooks for TLB-shootdown. When
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* unmapping a portion of the virtual address space, these hooks are called according to
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* the following template:
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*
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* tlb <- tlb_gather_mmu(mm, full_mm_flush); // start unmap for address space MM
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* {
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* for each vma that needs a shootdown do {
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* tlb_start_vma(tlb, vma);
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* for each page-table-entry PTE that needs to be removed do {
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* tlb_remove_tlb_entry(tlb, pte, address);
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* if (pte refers to a normal page) {
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* tlb_remove_page(tlb, page);
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* }
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* }
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* tlb_end_vma(tlb, vma);
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* }
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* }
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* tlb_finish_mmu(tlb, start, end); // finish unmap for address space MM
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*/
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#include <linux/mm.h>
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#include <linux/pagemap.h>
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#include <linux/swap.h>
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#include <asm/pgalloc.h>
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#include <asm/processor.h>
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#include <asm/tlbflush.h>
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#include <asm/machvec.h>
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#ifdef CONFIG_SMP
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# define FREE_PTE_NR 2048
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# define tlb_fast_mode(tlb) ((tlb)->nr == ~0U)
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#else
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# define FREE_PTE_NR 0
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# define tlb_fast_mode(tlb) (1)
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#endif
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struct mmu_gather {
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struct mm_struct *mm;
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unsigned int nr; /* == ~0U => fast mode */
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unsigned char fullmm; /* non-zero means full mm flush */
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unsigned char need_flush; /* really unmapped some PTEs? */
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unsigned long start_addr;
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unsigned long end_addr;
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struct page *pages[FREE_PTE_NR];
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};
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struct ia64_tr_entry {
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u64 ifa;
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u64 itir;
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u64 pte;
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u64 rr;
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}; /*Record for tr entry!*/
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extern int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size);
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extern void ia64_ptr_entry(u64 target_mask, int slot);
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extern struct ia64_tr_entry __per_cpu_idtrs[NR_CPUS][2][IA64_TR_ALLOC_MAX];
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/*
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region register macros
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*/
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#define RR_TO_VE(val) (((val) >> 0) & 0x0000000000000001)
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#define RR_VE(val) (((val) & 0x0000000000000001) << 0)
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#define RR_VE_MASK 0x0000000000000001L
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#define RR_VE_SHIFT 0
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#define RR_TO_PS(val) (((val) >> 2) & 0x000000000000003f)
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#define RR_PS(val) (((val) & 0x000000000000003f) << 2)
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#define RR_PS_MASK 0x00000000000000fcL
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#define RR_PS_SHIFT 2
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#define RR_RID_MASK 0x00000000ffffff00L
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#define RR_TO_RID(val) ((val >> 8) & 0xffffff)
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/* Users of the generic TLB shootdown code must declare this storage space. */
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DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
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/*
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* Flush the TLB for address range START to END and, if not in fast mode, release the
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* freed pages that where gathered up to this point.
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*/
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static inline void
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ia64_tlb_flush_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
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{
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unsigned int nr;
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if (!tlb->need_flush)
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return;
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tlb->need_flush = 0;
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if (tlb->fullmm) {
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/*
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* Tearing down the entire address space. This happens both as a result
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* of exit() and execve(). The latter case necessitates the call to
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* flush_tlb_mm() here.
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*/
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flush_tlb_mm(tlb->mm);
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} else if (unlikely (end - start >= 1024*1024*1024*1024UL
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|| REGION_NUMBER(start) != REGION_NUMBER(end - 1)))
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{
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/*
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* If we flush more than a tera-byte or across regions, we're probably
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* better off just flushing the entire TLB(s). This should be very rare
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* and is not worth optimizing for.
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*/
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flush_tlb_all();
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} else {
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/*
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* XXX fix me: flush_tlb_range() should take an mm pointer instead of a
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* vma pointer.
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*/
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struct vm_area_struct vma;
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vma.vm_mm = tlb->mm;
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/* flush the address range from the tlb: */
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flush_tlb_range(&vma, start, end);
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/* now flush the virt. page-table area mapping the address range: */
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flush_tlb_range(&vma, ia64_thash(start), ia64_thash(end));
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}
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/* lastly, release the freed pages */
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nr = tlb->nr;
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if (!tlb_fast_mode(tlb)) {
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unsigned long i;
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tlb->nr = 0;
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tlb->start_addr = ~0UL;
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for (i = 0; i < nr; ++i)
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free_page_and_swap_cache(tlb->pages[i]);
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}
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}
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/*
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* Return a pointer to an initialized struct mmu_gather.
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*/
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static inline struct mmu_gather *
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tlb_gather_mmu (struct mm_struct *mm, unsigned int full_mm_flush)
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{
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struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
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tlb->mm = mm;
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/*
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* Use fast mode if only 1 CPU is online.
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*
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* It would be tempting to turn on fast-mode for full_mm_flush as well. But this
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* doesn't work because of speculative accesses and software prefetching: the page
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* table of "mm" may (and usually is) the currently active page table and even
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* though the kernel won't do any user-space accesses during the TLB shoot down, a
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* compiler might use speculation or lfetch.fault on what happens to be a valid
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* user-space address. This in turn could trigger a TLB miss fault (or a VHPT
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* walk) and re-insert a TLB entry we just removed. Slow mode avoids such
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* problems. (We could make fast-mode work by switching the current task to a
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* different "mm" during the shootdown.) --davidm 08/02/2002
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*/
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tlb->nr = (num_online_cpus() == 1) ? ~0U : 0;
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tlb->fullmm = full_mm_flush;
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tlb->start_addr = ~0UL;
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return tlb;
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}
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/*
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* Called at the end of the shootdown operation to free up any resources that were
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* collected.
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*/
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static inline void
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tlb_finish_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
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{
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/*
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* Note: tlb->nr may be 0 at this point, so we can't rely on tlb->start_addr and
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* tlb->end_addr.
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*/
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ia64_tlb_flush_mmu(tlb, start, end);
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/* keep the page table cache within bounds */
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check_pgt_cache();
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put_cpu_var(mmu_gathers);
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}
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/*
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* Logically, this routine frees PAGE. On MP machines, the actual freeing of the page
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* must be delayed until after the TLB has been flushed (see comments at the beginning of
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* this file).
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*/
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static inline void
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tlb_remove_page (struct mmu_gather *tlb, struct page *page)
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{
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tlb->need_flush = 1;
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if (tlb_fast_mode(tlb)) {
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free_page_and_swap_cache(page);
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return;
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}
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tlb->pages[tlb->nr++] = page;
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if (tlb->nr >= FREE_PTE_NR)
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ia64_tlb_flush_mmu(tlb, tlb->start_addr, tlb->end_addr);
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}
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/*
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* Remove TLB entry for PTE mapped at virtual address ADDRESS. This is called for any
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* PTE, not just those pointing to (normal) physical memory.
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*/
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static inline void
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__tlb_remove_tlb_entry (struct mmu_gather *tlb, pte_t *ptep, unsigned long address)
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{
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if (tlb->start_addr == ~0UL)
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tlb->start_addr = address;
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tlb->end_addr = address + PAGE_SIZE;
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}
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#define tlb_migrate_finish(mm) platform_tlb_migrate_finish(mm)
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#define tlb_start_vma(tlb, vma) do { } while (0)
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#define tlb_end_vma(tlb, vma) do { } while (0)
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#define tlb_remove_tlb_entry(tlb, ptep, addr) \
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do { \
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tlb->need_flush = 1; \
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__tlb_remove_tlb_entry(tlb, ptep, addr); \
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} while (0)
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#define pte_free_tlb(tlb, ptep) \
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do { \
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tlb->need_flush = 1; \
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__pte_free_tlb(tlb, ptep); \
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} while (0)
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#define pmd_free_tlb(tlb, ptep) \
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do { \
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tlb->need_flush = 1; \
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__pmd_free_tlb(tlb, ptep); \
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} while (0)
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#define pud_free_tlb(tlb, pudp) \
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do { \
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tlb->need_flush = 1; \
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__pud_free_tlb(tlb, pudp); \
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} while (0)
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#endif /* _ASM_IA64_TLB_H */
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