553 lines
13 KiB
C
553 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2020 MediaTek Inc.
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#include <linux/delay.h>
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#include <linux/i2c.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <media/v4l2-async.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-fwnode.h>
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#include <media/v4l2-subdev.h>
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#define DW9768_NAME "dw9768"
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#define DW9768_MAX_FOCUS_POS (1024 - 1)
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/*
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* This sets the minimum granularity for the focus positions.
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* A value of 1 gives maximum accuracy for a desired focus position
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*/
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#define DW9768_FOCUS_STEPS 1
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/*
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* Ring control and Power control register
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* Bit[1] RING_EN
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* 0: Direct mode
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* 1: AAC mode (ringing control mode)
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* Bit[0] PD
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* 0: Normal operation mode
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* 1: Power down mode
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* DW9768 requires waiting time of Topr after PD reset takes place.
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*/
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#define DW9768_RING_PD_CONTROL_REG 0x02
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#define DW9768_PD_MODE_OFF 0x00
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#define DW9768_PD_MODE_EN BIT(0)
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#define DW9768_AAC_MODE_EN BIT(1)
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/*
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* DW9768 separates two registers to control the VCM position.
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* One for MSB value, another is LSB value.
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* DAC_MSB: D[9:8] (ADD: 0x03)
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* DAC_LSB: D[7:0] (ADD: 0x04)
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* D[9:0] DAC data input: positive output current = D[9:0] / 1023 * 100[mA]
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*/
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#define DW9768_MSB_ADDR 0x03
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#define DW9768_LSB_ADDR 0x04
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#define DW9768_STATUS_ADDR 0x05
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/*
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* AAC mode control & prescale register
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* Bit[7:5] Namely AC[2:0], decide the VCM mode and operation time.
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* 001 AAC2 0.48 x Tvib
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* 010 AAC3 0.70 x Tvib
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* 011 AAC4 0.75 x Tvib
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* 101 AAC8 1.13 x Tvib
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* Bit[2:0] Namely PRESC[2:0], set the internal clock dividing rate as follow.
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* 000 2
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* 001 1
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* 010 1/2
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* 011 1/4
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* 100 8
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* 101 4
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*/
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#define DW9768_AAC_PRESC_REG 0x06
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#define DW9768_AAC_MODE_SEL_MASK GENMASK(7, 5)
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#define DW9768_CLOCK_PRE_SCALE_SEL_MASK GENMASK(2, 0)
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/*
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* VCM period of vibration register
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* Bit[5:0] Defined as VCM rising periodic time (Tvib) together with PRESC[2:0]
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* Tvib = (6.3ms + AACT[5:0] * 0.1ms) * Dividing Rate
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* Dividing Rate is the internal clock dividing rate that is defined at
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* PRESCALE register (ADD: 0x06)
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*/
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#define DW9768_AAC_TIME_REG 0x07
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/*
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* DW9768 requires waiting time (delay time) of t_OPR after power-up,
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* or in the case of PD reset taking place.
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*/
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#define DW9768_T_OPR_US 1000
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#define DW9768_TVIB_MS_BASE10 (64 - 1)
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#define DW9768_AAC_MODE_DEFAULT 2
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#define DW9768_AAC_TIME_DEFAULT 0x20
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#define DW9768_CLOCK_PRE_SCALE_DEFAULT 1
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/*
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* This acts as the minimum granularity of lens movement.
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* Keep this value power of 2, so the control steps can be
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* uniformly adjusted for gradual lens movement, with desired
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* number of control steps.
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*/
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#define DW9768_MOVE_STEPS 16
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static const char * const dw9768_supply_names[] = {
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"vin", /* Digital I/O power */
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"vdd", /* Digital core power */
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};
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/* dw9768 device structure */
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struct dw9768 {
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struct regulator_bulk_data supplies[ARRAY_SIZE(dw9768_supply_names)];
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struct v4l2_ctrl_handler ctrls;
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struct v4l2_ctrl *focus;
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struct v4l2_subdev sd;
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u32 aac_mode;
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u32 aac_timing;
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u32 clock_presc;
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u32 move_delay_us;
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};
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static inline struct dw9768 *sd_to_dw9768(struct v4l2_subdev *subdev)
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{
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return container_of(subdev, struct dw9768, sd);
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}
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struct regval_list {
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u8 reg_num;
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u8 value;
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};
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struct dw9768_aac_mode_ot_multi {
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u32 aac_mode_enum;
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u32 ot_multi_base100;
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};
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struct dw9768_clk_presc_dividing_rate {
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u32 clk_presc_enum;
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u32 dividing_rate_base100;
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};
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static const struct dw9768_aac_mode_ot_multi aac_mode_ot_multi[] = {
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{1, 48},
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{2, 70},
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{3, 75},
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{5, 113},
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};
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static const struct dw9768_clk_presc_dividing_rate presc_dividing_rate[] = {
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{0, 200},
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{1, 100},
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{2, 50},
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{3, 25},
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{4, 800},
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{5, 400},
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};
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static u32 dw9768_find_ot_multi(u32 aac_mode_param)
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{
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u32 cur_ot_multi_base100 = 70;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(aac_mode_ot_multi); i++) {
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if (aac_mode_ot_multi[i].aac_mode_enum == aac_mode_param) {
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cur_ot_multi_base100 =
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aac_mode_ot_multi[i].ot_multi_base100;
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}
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}
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return cur_ot_multi_base100;
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}
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static u32 dw9768_find_dividing_rate(u32 presc_param)
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{
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u32 cur_clk_dividing_rate_base100 = 100;
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(presc_dividing_rate); i++) {
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if (presc_dividing_rate[i].clk_presc_enum == presc_param) {
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cur_clk_dividing_rate_base100 =
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presc_dividing_rate[i].dividing_rate_base100;
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}
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}
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return cur_clk_dividing_rate_base100;
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}
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/*
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* DW9768_AAC_PRESC_REG & DW9768_AAC_TIME_REG determine VCM operation time.
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* For current VCM mode: AAC3, Operation Time would be 0.70 x Tvib.
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* Tvib = (6.3ms + AACT[5:0] * 0.1MS) * Dividing Rate.
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* Below is calculation of the operation delay for each step.
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*/
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static inline u32 dw9768_cal_move_delay(u32 aac_mode_param, u32 presc_param,
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u32 aac_timing_param)
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{
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u32 Tvib_us;
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u32 ot_multi_base100;
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u32 clk_dividing_rate_base100;
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ot_multi_base100 = dw9768_find_ot_multi(aac_mode_param);
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clk_dividing_rate_base100 = dw9768_find_dividing_rate(presc_param);
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Tvib_us = (DW9768_TVIB_MS_BASE10 + aac_timing_param) *
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clk_dividing_rate_base100;
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return Tvib_us * ot_multi_base100 / 100;
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}
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static int dw9768_mod_reg(struct dw9768 *dw9768, u8 reg, u8 mask, u8 val)
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{
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struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
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int ret;
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ret = i2c_smbus_read_byte_data(client, reg);
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if (ret < 0)
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return ret;
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val = ((unsigned char)ret & ~mask) | (val & mask);
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return i2c_smbus_write_byte_data(client, reg, val);
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}
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static int dw9768_set_dac(struct dw9768 *dw9768, u16 val)
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{
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struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
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/* Write VCM position to registers */
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return i2c_smbus_write_word_swapped(client, DW9768_MSB_ADDR, val);
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}
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static int dw9768_init(struct dw9768 *dw9768)
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{
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struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
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int ret, val;
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/* Reset DW9768_RING_PD_CONTROL_REG to default status 0x00 */
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ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG,
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DW9768_PD_MODE_OFF);
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if (ret < 0)
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return ret;
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/*
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* DW9769 requires waiting delay time of t_OPR
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* after PD reset takes place.
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*/
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usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100);
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/* Set DW9768_RING_PD_CONTROL_REG to DW9768_AAC_MODE_EN(0x01) */
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ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG,
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DW9768_AAC_MODE_EN);
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if (ret < 0)
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return ret;
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/* Set AAC mode */
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ret = dw9768_mod_reg(dw9768, DW9768_AAC_PRESC_REG,
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DW9768_AAC_MODE_SEL_MASK,
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dw9768->aac_mode << 5);
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if (ret < 0)
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return ret;
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/* Set clock presc */
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if (dw9768->clock_presc != DW9768_CLOCK_PRE_SCALE_DEFAULT) {
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ret = dw9768_mod_reg(dw9768, DW9768_AAC_PRESC_REG,
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DW9768_CLOCK_PRE_SCALE_SEL_MASK,
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dw9768->clock_presc);
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if (ret < 0)
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return ret;
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}
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/* Set AAC Timing */
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if (dw9768->aac_timing != DW9768_AAC_TIME_DEFAULT) {
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ret = i2c_smbus_write_byte_data(client, DW9768_AAC_TIME_REG,
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dw9768->aac_timing);
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if (ret < 0)
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return ret;
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}
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for (val = dw9768->focus->val % DW9768_MOVE_STEPS;
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val <= dw9768->focus->val;
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val += DW9768_MOVE_STEPS) {
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ret = dw9768_set_dac(dw9768, val);
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if (ret) {
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dev_err(&client->dev, "I2C failure: %d", ret);
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return ret;
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}
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usleep_range(dw9768->move_delay_us,
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dw9768->move_delay_us + 1000);
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}
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return 0;
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}
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static int dw9768_release(struct dw9768 *dw9768)
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{
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struct i2c_client *client = v4l2_get_subdevdata(&dw9768->sd);
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int ret, val;
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val = round_down(dw9768->focus->val, DW9768_MOVE_STEPS);
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for ( ; val >= 0; val -= DW9768_MOVE_STEPS) {
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ret = dw9768_set_dac(dw9768, val);
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if (ret) {
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dev_err(&client->dev, "I2C write fail: %d", ret);
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return ret;
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}
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usleep_range(dw9768->move_delay_us,
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dw9768->move_delay_us + 1000);
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}
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ret = i2c_smbus_write_byte_data(client, DW9768_RING_PD_CONTROL_REG,
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DW9768_PD_MODE_EN);
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if (ret < 0)
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return ret;
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/*
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* DW9769 requires waiting delay time of t_OPR
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* after PD reset takes place.
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*/
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usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100);
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return 0;
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}
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static int dw9768_runtime_suspend(struct device *dev)
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{
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struct v4l2_subdev *sd = dev_get_drvdata(dev);
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struct dw9768 *dw9768 = sd_to_dw9768(sd);
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dw9768_release(dw9768);
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regulator_bulk_disable(ARRAY_SIZE(dw9768_supply_names),
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dw9768->supplies);
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return 0;
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}
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static int dw9768_runtime_resume(struct device *dev)
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{
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struct v4l2_subdev *sd = dev_get_drvdata(dev);
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struct dw9768 *dw9768 = sd_to_dw9768(sd);
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int ret;
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ret = regulator_bulk_enable(ARRAY_SIZE(dw9768_supply_names),
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dw9768->supplies);
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if (ret < 0) {
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dev_err(dev, "failed to enable regulators\n");
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return ret;
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}
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/*
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* The datasheet refers to t_OPR that needs to be waited before sending
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* I2C commands after power-up.
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*/
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usleep_range(DW9768_T_OPR_US, DW9768_T_OPR_US + 100);
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ret = dw9768_init(dw9768);
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if (ret < 0)
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goto disable_regulator;
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return 0;
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disable_regulator:
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regulator_bulk_disable(ARRAY_SIZE(dw9768_supply_names),
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dw9768->supplies);
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return ret;
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}
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static int dw9768_set_ctrl(struct v4l2_ctrl *ctrl)
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{
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struct dw9768 *dw9768 = container_of(ctrl->handler,
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struct dw9768, ctrls);
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if (ctrl->id == V4L2_CID_FOCUS_ABSOLUTE)
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return dw9768_set_dac(dw9768, ctrl->val);
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return 0;
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}
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static const struct v4l2_ctrl_ops dw9768_ctrl_ops = {
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.s_ctrl = dw9768_set_ctrl,
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};
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static int dw9768_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
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{
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int ret;
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ret = pm_runtime_get_sync(sd->dev);
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if (ret < 0) {
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pm_runtime_put_noidle(sd->dev);
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return ret;
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}
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return 0;
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}
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static int dw9768_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
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{
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pm_runtime_put(sd->dev);
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return 0;
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}
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static const struct v4l2_subdev_internal_ops dw9768_int_ops = {
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.open = dw9768_open,
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.close = dw9768_close,
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};
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static const struct v4l2_subdev_ops dw9768_ops = { };
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static int dw9768_init_controls(struct dw9768 *dw9768)
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{
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struct v4l2_ctrl_handler *hdl = &dw9768->ctrls;
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const struct v4l2_ctrl_ops *ops = &dw9768_ctrl_ops;
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v4l2_ctrl_handler_init(hdl, 1);
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dw9768->focus = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_ABSOLUTE, 0,
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DW9768_MAX_FOCUS_POS,
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DW9768_FOCUS_STEPS, 0);
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if (hdl->error)
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return hdl->error;
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dw9768->sd.ctrl_handler = hdl;
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return 0;
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}
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static int dw9768_probe(struct i2c_client *client)
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{
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struct device *dev = &client->dev;
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struct dw9768 *dw9768;
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unsigned int i;
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int ret;
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dw9768 = devm_kzalloc(dev, sizeof(*dw9768), GFP_KERNEL);
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if (!dw9768)
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return -ENOMEM;
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/* Initialize subdev */
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v4l2_i2c_subdev_init(&dw9768->sd, client, &dw9768_ops);
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dw9768->aac_mode = DW9768_AAC_MODE_DEFAULT;
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dw9768->aac_timing = DW9768_AAC_TIME_DEFAULT;
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dw9768->clock_presc = DW9768_CLOCK_PRE_SCALE_DEFAULT;
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/* Optional indication of AAC mode select */
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fwnode_property_read_u32(dev_fwnode(dev), "dongwoon,aac-mode",
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&dw9768->aac_mode);
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/* Optional indication of clock pre-scale select */
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fwnode_property_read_u32(dev_fwnode(dev), "dongwoon,clock-presc",
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&dw9768->clock_presc);
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/* Optional indication of AAC Timing */
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fwnode_property_read_u32(dev_fwnode(dev), "dongwoon,aac-timing",
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&dw9768->aac_timing);
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dw9768->move_delay_us = dw9768_cal_move_delay(dw9768->aac_mode,
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dw9768->clock_presc,
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dw9768->aac_timing);
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for (i = 0; i < ARRAY_SIZE(dw9768_supply_names); i++)
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dw9768->supplies[i].supply = dw9768_supply_names[i];
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ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dw9768_supply_names),
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dw9768->supplies);
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if (ret) {
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dev_err(dev, "failed to get regulators\n");
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return ret;
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}
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/* Initialize controls */
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ret = dw9768_init_controls(dw9768);
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if (ret)
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goto err_free_handler;
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/* Initialize subdev */
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dw9768->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
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dw9768->sd.internal_ops = &dw9768_int_ops;
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ret = media_entity_pads_init(&dw9768->sd.entity, 0, NULL);
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if (ret < 0)
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goto err_free_handler;
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dw9768->sd.entity.function = MEDIA_ENT_F_LENS;
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pm_runtime_enable(dev);
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if (!pm_runtime_enabled(dev)) {
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ret = dw9768_runtime_resume(dev);
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if (ret < 0) {
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dev_err(dev, "failed to power on: %d\n", ret);
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goto err_clean_entity;
|
|
}
|
|
}
|
|
|
|
ret = v4l2_async_register_subdev(&dw9768->sd);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to register V4L2 subdev: %d", ret);
|
|
goto err_power_off;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_power_off:
|
|
if (pm_runtime_enabled(dev))
|
|
pm_runtime_disable(dev);
|
|
else
|
|
dw9768_runtime_suspend(dev);
|
|
err_clean_entity:
|
|
media_entity_cleanup(&dw9768->sd.entity);
|
|
err_free_handler:
|
|
v4l2_ctrl_handler_free(&dw9768->ctrls);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dw9768_remove(struct i2c_client *client)
|
|
{
|
|
struct v4l2_subdev *sd = i2c_get_clientdata(client);
|
|
struct dw9768 *dw9768 = sd_to_dw9768(sd);
|
|
|
|
v4l2_async_unregister_subdev(&dw9768->sd);
|
|
v4l2_ctrl_handler_free(&dw9768->ctrls);
|
|
media_entity_cleanup(&dw9768->sd.entity);
|
|
pm_runtime_disable(&client->dev);
|
|
if (!pm_runtime_status_suspended(&client->dev))
|
|
dw9768_runtime_suspend(&client->dev);
|
|
pm_runtime_set_suspended(&client->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id dw9768_of_table[] = {
|
|
{ .compatible = "dongwoon,dw9768" },
|
|
{ .compatible = "giantec,gt9769" },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, dw9768_of_table);
|
|
|
|
static const struct dev_pm_ops dw9768_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
pm_runtime_force_resume)
|
|
SET_RUNTIME_PM_OPS(dw9768_runtime_suspend, dw9768_runtime_resume, NULL)
|
|
};
|
|
|
|
static struct i2c_driver dw9768_i2c_driver = {
|
|
.driver = {
|
|
.name = DW9768_NAME,
|
|
.pm = &dw9768_pm_ops,
|
|
.of_match_table = dw9768_of_table,
|
|
},
|
|
.probe_new = dw9768_probe,
|
|
.remove = dw9768_remove,
|
|
};
|
|
module_i2c_driver(dw9768_i2c_driver);
|
|
|
|
MODULE_AUTHOR("Dongchun Zhu <dongchun.zhu@mediatek.com>");
|
|
MODULE_DESCRIPTION("DW9768 VCM driver");
|
|
MODULE_LICENSE("GPL v2");
|